The request id is updated to 0 when the substate is
BUBBLE, then the original request id can't be notified
to UMD, since the reported_req_id is already updated to
the original request id. This change updateds the
reported_req_id only when the final request id is
valid.
CRs-Fixed: 2932602
Change-Id: Ib30f849782283c647f784cfb0deb49bee3d04287
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
Change module tag from SFE to ISP in IFE bus file.
Also update error code to success for bus debug config.
CRs-Fixed: 2841729
Change-Id: I0c648aeef2864cd55a0940c73235087c7de9d910
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Prevent potential errors on starting path after flush by issuing start
command after configuring RX.
CRs-Fixed: 2846451
Change-Id: Ib72fc9f0b8397f360f5bed73379ec65310cdc609
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
During disabling the CSI2, do not reset the rx registers to 0.
This can result in random behaviors if the phy is streaming.
Just disable the IRQs and let the stream off call handle the
reset part.
CRs-Fixed: 2946879
Change-Id: I936ea4026c72033a665958281d7f07751b4ae708
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Fixes for the issues found in Unit testing of CRE.
CRs-Fixed: 2893978
Change-Id: I7b8061cf2fd4693bde084a003bc101be1cbde1d1
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
Modify check for multi vc-dt. The change also programs the
right value for dynamic switch select.
CRs-Fixed: 2841729
Change-Id: I9b7459f77d65a83f3d559967a04d81357f7c6de3
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Change mode of all RDI WMs to line based mode to account for
SFE ZSL RAW 80 byte stride alignment. This change is to make
it generic for all RAW outputs. If the mode needs to be made
frame based, userland will override it.
CRs-Fixed: 2841729
Change-Id: I87705c2b035df905d76fbbe80e170991c2230135
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Lane enable needs to be program with header tag LANE_ENABLE. This
change adds the tag associated with the correct register offset.
CRs-Fixed: 2929063
Change-Id: Ibbb8e4e0fc2d2de8e9c9f193b3d31ba5492b22f4
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Add support to dump the 3ph and 2ph specific
status registers. Following debugfs command can
be used to enable status register dump for csiphy0:
adb shell
"echo 1>/sys/kernel/debug/camera_csiphy/csiphy0_en_status_reg_dump"
CRs-Fixed: 2942364
Change-Id: If8d57a9e54c9e509de35f6a57d7baa1895be7779
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
It's possible that for a given use-case the pipeline is
CSID2->SFE0->IFE2, in the event of an overflow we need to log
the right SFE's debug registers. Unlike IFE we cannot use
CSID hw_idx to find the SFE core in the pipeline. The change
ensures we log the connected SFE core's debug registers.
CRs-Fixed: 2841729
Change-Id: I2beda7496b95a2b7c1aafc8cfcfcdde662c31898
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Device enabled flag is not set during stop preventing the
buf done irq mask to be set during next start without disabling
the core.
This commit adds device_enabled flag to false during csid stop
call.
CRs-Fixed: 2943893
Change-Id: Ic9c6a86219a6e3761b50817c94c0e6b89a6fde95
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Add Support to program the output_bus_select register
at the end of programming all the lanes.
CRs-Fixed: 2942604
Change-Id: I0279aa6bc824b75e3df1c62c3f69d146ec80b356
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
Clean up unused variables from the csiphy code. Also,
update the code for better readability.
CRs-Fixed: 2942364
Change-Id: I601e06fd8a61607a69390c10124a70f2c7e60dd8
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
Add 128 bit width support for RDI WM.
Add rdi_width in the HW based register header file.
Based on this rdi_width set RDI width for RDI WM.
CRs-Fixed: 2944087
Change-Id: I941229141822e499fce0ef6ef30012345d463529
Signed-off-by: Wyes Karny <wkarny@codeaurora.org>
In stability test cases, it is possible that some CSID hw registers
is accessed after being power down.
This adds state checks before accessing the CSID hw registers.
Change-Id: I1b5d7873f58f2e21043338037b82c233fa773de9
CRs-Fixed: 2934815
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
In dual IFE case, HW reset times out because completion struct gets
reinited after reset IRQ is received and before going into wait. During
SW reset, 3 IRQs are observed, 2 during master reset and 1 during slave.
This can cause the done count in the completion struct to be increment
by 1 for the slave CSID during SW reset and result in incorrect
reporting of IRQs during the next reset call.
To solve this problem, there are two reinit_completion calls:
1. Pre-reset command: Only for SW reset. This is to clear the
completion struct in the cases of HW reset timeout followed by
reset IRQ or slave reset IRQ triggerred by master.
2. Post-reset command: For both HW and SW reset. This is to
clear the completion struct after successful reset command to
use it again during next reset.
CRs-Fixed: 2846451
Change-Id: I6d416a63e6d7e3828e55d1deece56b38a349f99f
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
Flag fatal_err_detected is getting set for recoverable errors
as well. This causes false propagation of errors.
This commit removes the handling of recoverable errors as fatal.
CRs-Fixed: 2940802
Change-Id: I25710287efe918d8f97618ca24eea57378abed3c
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
This is a fix to handle line corruption on RDI stream by giving more
priority to IFE traffic. This is specific to SHIMA CAMNOC design.
- Set Priority for IFE (RT) stream to P6.
- OT = 55 for IPE RD.
- IPE clk to be capped to SVS.
CRs-Fixed: 2887253
Change-Id: Ica574742052f018e94072240a0fd1d08be223727
Signed-off-by: Alok Pandey <akumarpa@codeaurora.org>
Before powering down Top HM, qchannel handshake needs to be
done to ensure camnoc is idle. Add qchannel register info
to enable handshake on v680 hardware.
CRs-Fixed: 2841729
Change-Id: I55c240dc0f780fb5f8339dbd0a2d9aa4ef280be4
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Currently, clock update function is same between different
vfe top versions. Move clock voting functions to common
top to avoid duplication.
CRs-Fixed: 2841729
Change-Id: I2504632a260ea18f8b5e38e65395db95375588bb
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Currently, camnoc buffer fill level register offsets are part
of cpas monitoring. Register offsets keep changing between
targets which would bring more conditionals. Make cpas monitoring
generic by moving register offsets to header. Also, the reg values
will be read in a buffer, and it can be controlled what offset
needs to be read, by changing status in header to be enable/disable.
Also, move camnoc fill level printing to CPAS for when we need only
buffer fill info.
CRs-Fixed: 2841729
Change-Id: I05425b4466d33dbef80eb8a0a1b5e974a6965600
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
