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@@ -84,28 +84,24 @@ struct cam_csiphy_aon_sel_params_t {
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/**
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* struct csiphy_reg_parms_t
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- * @mipi_csiphy_glbl_irq_cmd_addr: CSIPhy irq addr
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- * @mipi_csiphy_interrupt_status0_addr:
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- * CSIPhy interrupt status addr
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- * @mipi_csiphy_interrupt_mask0_addr:
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- * CSIPhy interrupt mask addr
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- * @mipi_csiphy_interrupt_mask_val:
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- * CSIPhy interrupt mask val
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- * @mipi_csiphy_interrupt_clear0_addr:
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- * CSIPhy interrupt clear addr
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- * @csiphy_version: CSIPhy Version
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- * @csiphy_common_array_size: CSIPhy common array size
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- * @csiphy_reset_array_size: CSIPhy reset array size
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- * @csiphy_2ph_config_array_size: 2ph settings size
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- * @csiphy_3ph_config_array_size: 3ph settings size
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- * @csiphy_cpas_cp_bits_per_phy: CP bits per phy
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- * @csiphy_cpas_cp_is_interleaved: checks whether cp bits
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- * are interleaved or not
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- * @csiphy_cpas_cp_2ph_offset: cp register 2ph offset
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- * @csiphy_cpas_cp_3ph_offset: cp register 3ph offset
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- * @csiphy_2ph_clock_lane: clock lane in 2ph
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- * @csiphy_2ph_combo_ck_ln: clk lane in combo 2ph
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- * @aon_sel_params: aon selection parameters
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+ * @mipi_csiphy_glbl_irq_cmd_addr : CSIPhy irq addr
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+ * @mipi_csiphy_interrupt_status0_addr: CSIPhy interrupt status addr
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+ * @mipi_csiphy_interrupt_mask0_addr : CSIPhy interrupt mask addr
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+ * @mipi_csiphy_interrupt_mask_val : CSIPhy interrupt mask val
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+ * @mipi_csiphy_interrupt_clear0_addr : CSIPhy interrupt clear addr
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+ * @csiphy_version : CSIPhy Version
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+ * @csiphy_common_array_size : CSIPhy common array size
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+ * @csiphy_reset_array_size : CSIPhy reset array size
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+ * @csiphy_2ph_config_array_size : 2ph settings size
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+ * @csiphy_3ph_config_array_size : 3ph settings size
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+ * @csiphy_cpas_cp_bits_per_phy : CP bits per phy
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+ * @csiphy_cpas_cp_is_interleaved : checks whether cp bits are interleaved
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+ * or not
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+ * @csiphy_cpas_cp_2ph_offset : cp register 2ph offset
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+ * @csiphy_cpas_cp_3ph_offset : cp register 3ph offset
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+ * @csiphy_2ph_clock_lane : clock lane in 2ph
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+ * @csiphy_2ph_combo_ck_ln : clk lane in combo 2ph
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+ * @aon_sel_params : aon selection parameters
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*/
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struct csiphy_reg_parms_t {
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/*MIPI CSI PHY registers*/
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@@ -134,8 +130,8 @@ struct csiphy_reg_parms_t {
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/**
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* struct csiphy_intf_params
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- * @device_hdl: Device Handle
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- * @session_hdl: Session Handle
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+ * @device_hdl : Device Handle
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+ * @session_hdl : Session Handle
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*/
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struct csiphy_hdl_tbl {
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int32_t device_hdl;
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@@ -144,10 +140,10 @@ struct csiphy_hdl_tbl {
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/**
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* struct csiphy_reg_t
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- * @reg_addr: Register address
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- * @reg_data: Register data
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- * @delay: Delay in us
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- * @csiphy_param_type: CSIPhy parameter type
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+ * @reg_addr : Register address
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+ * @reg_data : Register data
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+ * @delay : Delay in us
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+ * @csiphy_param_type : CSIPhy parameter type
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*/
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struct csiphy_reg_t {
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int32_t reg_addr;
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@@ -165,9 +161,9 @@ struct csiphy_cphy_per_lane_info {
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/*
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* struct data_rate_reg_info_t
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- * @bandwidth: max bandwidth supported by this reg settings
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+ * @bandwidth : max bandwidth supported by this reg settings
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* @data_rate_reg_array_size: number of reg value pairs in the array
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- * @csiphy_data_rate_regs: array of data rate specific reg value pairs
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+ * @csiphy_data_rate_regs : array of data rate specific reg value pairs
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*/
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struct data_rate_reg_info_t {
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uint64_t bandwidth;
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@@ -178,10 +174,10 @@ struct data_rate_reg_info_t {
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/**
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* struct data_rate_settings_t
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- * @num_data_rate_settings: number of valid settings
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- * present in the data rate settings array
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- * @data_rate_settings: array of regsettings which are specific to
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- * data rate
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+ * @num_data_rate_settings: Number of valid settings
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+ * present in the data rate settings array
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+ * @data_rate_settings : Array of regsettings which are specific to
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+ * data rate
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*/
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struct data_rate_settings_t {
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ssize_t num_data_rate_settings;
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@@ -190,21 +186,17 @@ struct data_rate_settings_t {
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/**
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* struct csiphy_ctrl_t
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- * @csiphy_reg: Register address
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- * @csiphy_common_reg: Common register set
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- * @csiphy_reset_reg: Reset register set
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- * @csiphy_2ph_reg: 2phase register set
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- * @csiphy_2ph_combo_mode_reg:
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- * 2phase combo register set
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- * @csiphy_3ph_reg: 3phase register set
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- * @csiphy_2ph_3ph_mode_reg:
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- * 2 phase 3phase combo register set
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- * @getclockvoting: function pointer which
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- * is used to find the clock voting
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- * for the sensor output data rate
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- * @data_rate_settings_table:
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- * Table which maintains the resgister
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- * settings specific to data rate
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+ * @csiphy_reg : Register address
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+ * @csiphy_common_reg : Common register set
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+ * @csiphy_reset_reg : Reset register set
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+ * @csiphy_2ph_reg : 2phase register set
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+ * @csiphy_2ph_combo_mode_reg : 2phase combo register set
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+ * @csiphy_3ph_reg : 3phase register set
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+ * @csiphy_2ph_3ph_mode_reg : 2 phase 3phase combo register set
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+ * @getclockvoting : function pointer which is used to find the clock
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+ * voting for the sensor output data rate
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+ * @data_rate_settings_table : Table which maintains the resgister settings
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+ * specific to data rate
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*/
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struct csiphy_ctrl_t {
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struct csiphy_reg_parms_t csiphy_reg;
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@@ -249,66 +241,59 @@ struct cam_csiphy_param {
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/**
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* struct csiphy_device
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- * @device_name: Device name
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- * @pdev: Platform device
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- * @irq: Interrupt structure
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- * @base: Base address
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- * @hw_version: Hardware Version
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- * @csiphy_state: CSIPhy state
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- * @ctrl_reg: CSIPhy control registers
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- * @num_clk: Number of clocks
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- * @csiphy_max_clk: Max timer clock rate
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- * @num_vreg: Number of regulators
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- * @csiphy_clk: Clock structure
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- * @csiphy_clk_info: Clock information structure
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- * @csiphy_vreg: Regulator structure
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- * @csiphy_reg_ptr: Regulator structure
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- * @csiphy_3p_clk_info: 3Phase clock information
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- * @csiphy_3p_clk: 3Phase clocks structure
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- * @csi_3phase: Is it a 3Phase mode
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- * @ref_count: Reference count
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- * @clk_lane: Clock lane
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- * @rx_clk_src_idx: Phy src clk index
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- * @acquire_count: Acquire device count
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- * @start_dev_count: Start count
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- * @soc_info: SOC information
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- * @cpas_handle: CPAS handle
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- * @current_data_rate: Data rate in mbps
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- * @csiphy_3phase: To identify DPHY or CPHY at top level
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- * @combo_mode: Info regarding combo_mode is enable / disable
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- * @ops: KMD operations
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- * @crm_cb: Callback API pointers
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- * @enable_irq_dump: Debugfs variable to enable hw IRQ register dump
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+ * @device_name : Device name
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+ * @mutex : ioctl operation mutex
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+ * @hw_version : Hardware Version
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+ * @clk_lane : Clock lane
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+ * @acquire_count : Acquire device count
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+ * @start_dev_count : Start count
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+ * @csiphy_max_clk : Max timer clock rate
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+ * @cpas_handle : CPAS handle
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+ * @session_max_device_support : Max number of devices supported in a session
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+ * @combo_mode : Info regarding combo_mode is enable / disable
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+ * @cphy_dphy_combo_mode : Info regarding 2ph/3ph combo modes
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+ * @rx_clk_src_idx : Phy src clk index
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+ * @is_divisor_32_comp : 32 bit hw compatibility
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+ * @csiphy_state : CSIPhy state
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+ * @ctrl_reg : CSIPhy control registers
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+ * @csiphy_3p_clk_info : 3Phase clock information
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+ * @csiphy_3p_clk : 3Phase clocks structure
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+ * @ref_count : Reference count
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+ * @v4l2_dev_str : V4L2 related data
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+ * @csiphy_info : Sensor specific csiphy info
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+ * @soc_info : SOC information
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+ * @current_data_rate : Data rate in mbps
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+ * @csiphy_cpas_cp_reg_mask : Secure csiphy lane mask
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+ * @ops : KMD operations
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+ * @crm_cb : Callback API pointers
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+ * @enable_irq_dump : Debugfs variable to enable hw IRQ register dump
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*/
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struct csiphy_device {
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char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
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struct mutex mutex;
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uint32_t hw_version;
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+ uint32_t clk_lane;
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+ uint32_t acquire_count;
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+ uint32_t start_dev_count;
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+ uint32_t csiphy_max_clk;
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+ uint32_t cpas_handle;
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+ uint8_t session_max_device_support;
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+ uint8_t combo_mode;
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+ uint8_t cphy_dphy_combo_mode;
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+ uint8_t rx_clk_src_idx;
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+ uint8_t is_divisor_32_comp;
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enum cam_csiphy_state csiphy_state;
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struct csiphy_ctrl_t *ctrl_reg;
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- uint32_t csiphy_max_clk;
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struct msm_cam_clk_info csiphy_3p_clk_info[2];
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struct clk *csiphy_3p_clk[2];
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int32_t ref_count;
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- uint16_t lane_mask[MAX_CSIPHY];
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- uint8_t is_csiphy_3phase_hw;
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- uint8_t is_divisor_32_comp;
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- uint8_t num_irq_registers;
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struct cam_subdev v4l2_dev_str;
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struct cam_csiphy_param csiphy_info[
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CSIPHY_MAX_INSTANCES_PER_PHY];
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- uint32_t clk_lane;
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- uint8_t rx_clk_src_idx;
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- uint32_t acquire_count;
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- uint32_t start_dev_count;
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struct cam_hw_soc_info soc_info;
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- uint32_t cpas_handle;
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uint64_t current_data_rate;
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uint64_t csiphy_cpas_cp_reg_mask[
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CSIPHY_MAX_INSTANCES_PER_PHY];
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- uint8_t session_max_device_support;
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- uint8_t combo_mode;
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- uint8_t cphy_dphy_combo_mode;
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struct cam_req_mgr_kmd_ops ops;
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struct cam_req_mgr_crm_cb *crm_cb;
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bool enable_irq_dump;
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