Merge "msm: camera: csiphy: Dump PHY Status Registers" into camera-kernel.lnx.5.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -98,6 +98,77 @@ void cam_csiphy_query_cap(struct csiphy_device *csiphy_dev,
 	csiphy_cap->clk_lane = csiphy_dev->clk_lane;
 }
 
+int cam_csiphy_print_status_reg(struct csiphy_device *csiphy_dev)
+{
+	struct cam_hw_soc_info *soc_info;
+	void __iomem *phybase = NULL;
+	void __iomem *lane0_offset = 0;
+	void __iomem *lane1_offset = 0;
+	void __iomem *lane2_offset = 0;
+	void __iomem *lane3_offset = 0;
+	struct csiphy_reg_parms_t *csiphy_reg;
+	struct cam_cphy_dphy_status_reg_params_t *status_regs;
+	int i = 0;
+
+	if (!csiphy_dev) {
+		CAM_ERR(CAM_CSIPHY, "Null csiphy_dev");
+		return -EINVAL;
+	}
+
+	soc_info = &csiphy_dev->soc_info;
+	if (!soc_info) {
+		CAM_ERR(CAM_CSIPHY, "Null soc_info");
+		return -EINVAL;
+	}
+
+	csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg;
+	status_regs = csiphy_reg->status_reg_params;
+	phybase = soc_info->reg_map[0].mem_base;
+
+	if (!status_regs) {
+		CAM_ERR(CAM_CSIPHY, "2ph/3ph status offset not set");
+		return -EINVAL;
+	}
+
+	if (g_phy_data[soc_info->index].is_3phase) {
+		CAM_INFO(CAM_CSIPHY, "Dumping 3ph status regs");
+		lane0_offset = phybase + status_regs->csiphy_3ph_status0_offset;
+		lane1_offset =
+			lane0_offset + csiphy_reg->size_offset_betn_lanes;
+		lane2_offset =
+			lane1_offset + csiphy_reg->size_offset_betn_lanes;
+
+		for (i = 0; i < status_regs->csiphy_3ph_status_size; i++) {
+			CAM_INFO(CAM_CSIPHY,
+				"PHY: %d, Status%u. Ln0: 0x%x, Ln1: 0x%x, Ln2: 0x%x",
+				soc_info->index, i,
+				cam_io_r(lane0_offset + (i * 4)),
+				cam_io_r(lane1_offset + (i * 4)),
+				cam_io_r(lane2_offset + (i * 4)));
+		}
+	} else {
+		CAM_INFO(CAM_CSIPHY, "Dumping 2ph status regs");
+		lane0_offset = phybase + status_regs->csiphy_2ph_status0_offset;
+		lane1_offset =
+			lane0_offset + csiphy_reg->size_offset_betn_lanes;
+		lane2_offset =
+			lane1_offset + csiphy_reg->size_offset_betn_lanes;
+		lane3_offset =
+			lane2_offset + csiphy_reg->size_offset_betn_lanes;
+
+		for (i = 0; i < status_regs->csiphy_2ph_status_size; i++) {
+			CAM_INFO(CAM_CSIPHY,
+				"PHY: %d, Status%u. Ln0: 0x%x, Ln1: 0x%x, Ln2: 0x%x, Ln3: 0x%x",
+				soc_info->index, i,
+				cam_io_r(lane0_offset + (i * 4)),
+				cam_io_r(lane1_offset + (i * 4)),
+				cam_io_r(lane2_offset + (i * 4)),
+				cam_io_r(lane3_offset + (i * 4)));
+		}
+	}
+	return 0;
+}
+
 void cam_csiphy_reset(struct csiphy_device *csiphy_dev)
 {
 	int32_t  i;
@@ -119,6 +190,11 @@ void cam_csiphy_reset(struct csiphy_device *csiphy_dev)
 			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay
 			+ 5);
 	}
+
+	if (csiphy_dev->en_status_reg_dump) {
+		CAM_INFO(CAM_CSIPHY, "Status Reg Dump after phy reset");
+		cam_csiphy_print_status_reg(csiphy_dev);
+	}
 }
 
 static void cam_csiphy_prgm_cmn_data(
@@ -1644,6 +1720,12 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			mutex_unlock(&active_csiphy_cnt_mutex);
 		}
 
+		if (csiphy_dev->en_status_reg_dump) {
+			usleep_range(50000, 50005);
+			CAM_INFO(CAM_CSIPHY, "Status Reg Dump after config");
+			cam_csiphy_print_status_reg(csiphy_dev);
+		}
+
 		CAM_DBG(CAM_CSIPHY, "START DEV CNT: %d",
 			csiphy_dev->start_dev_count);
 		csiphy_dev->csiphy_state = CAM_CSIPHY_START;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h

@@ -65,4 +65,11 @@ void cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev);
  *
  */
 int cam_csiphy_util_update_aon_ops(bool get_access, uint32_t phy_idx);
+
+/**
+ * @csiphy_dev: CSIPhy device structure
+ *
+ * This API allows to print all the cphy/dphy specific status registers
+ */
+int cam_csiphy_print_status_reg(struct csiphy_device *csiphy_dev);
 #endif /* _CAM_CSIPHY_CORE_H_ */

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c

@@ -10,6 +10,7 @@
 #include <media/cam_sensor.h>
 #include "camera_main.h"
 
+#define CSIPHY_DEBUGFS_NAME_MAX_SIZE 30
 static struct dentry *root_dentry;
 
 static void cam_csiphy_subdev_handle_message(
@@ -23,8 +24,15 @@ static void cam_csiphy_subdev_handle_message(
 	case CAM_SUBDEV_MESSAGE_IRQ_ERR:
 		CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d",
 				csiphy_dev->soc_info.index, data);
-		if (data == csiphy_dev->soc_info.index)
+		if (data == csiphy_dev->soc_info.index) {
 			cam_csiphy_status_dmp(csiphy_dev);
+
+			if (csiphy_dev->en_status_reg_dump) {
+				CAM_INFO(CAM_CSIPHY,
+					"Status Reg Dump on failure");
+				cam_csiphy_print_status_reg(csiphy_dev);
+			}
+		}
 		break;
 	default:
 		break;
@@ -35,7 +43,7 @@ static int cam_csiphy_debug_register(struct csiphy_device *csiphy_dev)
 {
 	int rc = 0;
 	struct dentry *dbgfileptr = NULL;
-	char debugfs_name[25];
+	char debugfs_name[CSIPHY_DEBUGFS_NAME_MAX_SIZE];
 
 	if (!csiphy_dev) {
 		CAM_ERR(CAM_CSIPHY, "null CSIPHY dev ptr");
@@ -54,12 +62,20 @@ static int cam_csiphy_debug_register(struct csiphy_device *csiphy_dev)
 		root_dentry = dbgfileptr;
 	}
 
-	snprintf(debugfs_name, 25, "%s%d%s", "csiphy",
+	snprintf(debugfs_name, CSIPHY_DEBUGFS_NAME_MAX_SIZE, "%s%d%s", "csiphy",
 		csiphy_dev->soc_info.index,
 		"_en_irq_dump");
 	dbgfileptr = debugfs_create_bool(debugfs_name, 0644,
 		root_dentry, &csiphy_dev->enable_irq_dump);
 
+	memset(debugfs_name, 0, CSIPHY_DEBUGFS_NAME_MAX_SIZE);
+
+	snprintf(debugfs_name, CSIPHY_DEBUGFS_NAME_MAX_SIZE, "%s%d%s", "csiphy",
+		csiphy_dev->soc_info.index,
+		"_en_status_reg_dump");
+	dbgfileptr = debugfs_create_bool(debugfs_name, 0644,
+		root_dentry, &csiphy_dev->en_status_reg_dump);
+
 	if (IS_ERR(dbgfileptr)) {
 		if (PTR_ERR(dbgfileptr) == -ENODEV)
 			CAM_WARN(CAM_CSIPHY, "DebugFS not enabled in kernel!");

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -82,10 +82,28 @@ struct cam_csiphy_aon_sel_params_t {
 	uint32_t mclk_sel_mask;
 };
 
+/**
+ * struct cam_cphy_dphy_status_reg_params_t
+ * @csiphy_3ph_status0_offset       : CSIPhy 3ph status addr
+ * @2ph_status0_offset              : CSIPhy 2ph status addr
+ * @3ph_status_size                 : CSIPhy 3ph status registers size
+ * @2ph_status_size                 : CSIPhy 2ph status registers size
+ */
+struct cam_cphy_dphy_status_reg_params_t {
+	uint32_t csiphy_3ph_status0_offset;
+	uint32_t csiphy_2ph_status0_offset;
+	uint16_t csiphy_3ph_status_size;
+	uint16_t csiphy_2ph_status_size;
+};
+
 /**
  * struct csiphy_reg_parms_t
  * @mipi_csiphy_glbl_irq_cmd_addr     : CSIPhy irq addr
  * @mipi_csiphy_interrupt_status0_addr: CSIPhy interrupt status addr
+ * @status_reg_params                 : Parameters to read cphy/dphy
+ *                                      specific status registers
+ * @size_offset_betn_lanes            : Size Offset between consecutive
+ *                                      2ph or 3ph lanes
  * @mipi_csiphy_interrupt_mask0_addr  : CSIPhy interrupt mask addr
  * @mipi_csiphy_interrupt_mask_val    : CSIPhy interrupt mask val
  * @mipi_csiphy_interrupt_clear0_addr : CSIPhy interrupt clear addr
@@ -107,6 +125,8 @@ struct csiphy_reg_parms_t {
 /*MIPI CSI PHY registers*/
 	uint32_t mipi_csiphy_glbl_irq_cmd_addr;
 	uint32_t mipi_csiphy_interrupt_status0_addr;
+	struct cam_cphy_dphy_status_reg_params_t *status_reg_params;
+	uint32_t size_offset_betn_lanes;
 	uint32_t mipi_csiphy_interrupt_mask0_addr;
 	uint32_t mipi_csiphy_interrupt_mask_val;
 	uint32_t mipi_csiphy_interrupt_mask_addr;
@@ -266,7 +286,9 @@ struct cam_csiphy_param {
  * @csiphy_cpas_cp_reg_mask    : Secure csiphy lane mask
  * @ops                        : KMD operations
  * @crm_cb                     : Callback API pointers
- * @enable_irq_dump            : Debugfs variable to enable hw IRQ register dump
+ * @enable_irq_dump            : Debugfs flag to enable hw IRQ register dump
+ * @en_status_reg_dump         : Debugfs flag to enable cphy/dphy specific
+ *                               status register dump
  */
 struct csiphy_device {
 	char                           device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
@@ -297,6 +319,7 @@ struct csiphy_device {
 	struct cam_req_mgr_kmd_ops     ops;
 	struct cam_req_mgr_crm_cb     *crm_cb;
 	bool                           enable_irq_dump;
+	bool                           en_status_reg_dump;
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_0 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_1 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 7,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_2 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 8,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
 	.csiphy_reset_array_size = 2,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_5_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_5 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 6,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v1_2 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 7,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h

@@ -12,6 +12,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x8B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x858,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
+	.status_reg_params = NULL,
+	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 8,
 	.csiphy_reset_array_size = 5,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -14,8 +14,17 @@ struct cam_csiphy_aon_sel_params_t aon_cam_select_params = {
 	.mclk_sel_mask = BIT(8),
 };
 
+struct cam_cphy_dphy_status_reg_params_t status_regs_2_1_0 = {
+	.csiphy_3ph_status0_offset = 0x340,
+	.csiphy_2ph_status0_offset = 0x00C0,
+	.csiphy_3ph_status_size = 24,
+	.csiphy_2ph_status_size = 20,
+};
+
 struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x10B0,
+	.status_reg_params = &status_regs_2_1_0,
+	.size_offset_betn_lanes = 0x400,
 	.mipi_csiphy_interrupt_clear0_addr = 0x1058,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x1028,
 	.csiphy_common_array_size = 5,