When PCIE linkdown happen, IRQ handler will disable IRQ line then
trigger SSR. disable_irq() is used but it introduce sleep in IRQ
context(unexpected). Crash will happen if CONFIG_SCHED_WALT is set:
android_rvh_schedule_bug+0x4/0x8
__might_sleep+0x50/0x84
synchronize_irq+0x48/0xc4
disable_irq+0x70/0x9c
cnss_pci_handle_linkdown+0x1a8/0x1c0 [cnss2]
cnss_pci_event_cb+0x148/0x348 [cnss2]
msm_pcie_notify_client+0x110/0x180
msm_pcie_handle_linkdown+0x2d8/0x2f8
handle_global_irq+0x464/0x5dc
To avoid this issue, should use disable_irq_nosync(), which doesn't
wait IRQ handler to finish. It should introduce no side effect, as
the whole device will be restated later by SSR.
Change-Id: I5ec96d41337a14280333ab9fea0c1f6132a532af
CRs-Fixed: 3548604
Move trivial repetitive logs from cnss IPC logs to
cnss-long IPC logs. This will reduce the chances of
losing important logs required for debug.
Change-Id: I9cfe76614603d5fb9b3e5d4a2f062abbb7fa754f
CRs-Fixed: 3580107
In current implementation, the error log not record the
return value of setting pci power function, with this return
value we can know the reason of why setting pci power failed.
Change-Id: Icf1fdba16faf539334704ca1f8ce24fecd49aa94
When feature CNSS2_CONDITIONAL_POWEROFF enabled, wlan chip HST and
HSP will not power off in cnss probe. PCI link will not be triggered
to retrain once CNSS2_ENUM_WITH_LOW_SPEED enabled.
So, add API cnss_pci_link_retrain_trigger() to trigger pci link retrain
when HST and HSP not power off.
Change-Id: I2ba44837a03b09b1ef3cd0c23a780b89ff837740
CRs-Fixed: 3491396
Complete power_up event on probe failure to avoid timeout while
waiting for this event during unregister of host driver.
Change-Id: Ie262305ef960ab40cd38b4a695d409eb36fcf0d7
CRs-Fixed: 3565756
PCI link info contains maximum link speed and link width
supported by platform. WLAN FW will use supported link
speed to restrict link speed switch upto maximum
supported speed.
Change-Id: Icdf54c8729192faf4966514b57bd826f86652065
CRs-Fixed: 3535790
In some scenarios, during force FW assert,
cnss_pci_pm_runtime_get_sync might not resume bus.
Make sure PCI bus is resume before accessing.
Change-Id: Ic5c17c3385318dbc739358ac7ccdb148aed1052a
CRs-Fixed: 3540601
With VT-d disabled on x86 platform, only one pci irq vector is allocated.
Due to the irq is not freed when suspend, the kernel will migrate irq to
CPU0 if it was affine to other CPU and then allocate a new MSI vector,
which cause the issue about no irq handler for vector once resume since
the driver only configure MSI data once during driver loading.
The fix is to set irq vector affinity to CPU0 before calling request_irq
to avoid the irq migration.
Change-Id: Id366e33113089f50899eb3631db66dcde0999d84
CRs-Fixed: 3550165
Send QMI message with TME-L patch information to WLAN FW, to
download TME-L patch.
Change-Id: Ieae07c0f761ada45ffcb990b1412654b9c6862b1
CRs-Fixed: 3521187
Host triggered force assert can be called asynchronous.
As part of force assert, CNSS dumps few MHI registers and
trigger RDDM asynchronously. There are chances of race between
force assert and runtime suspend.
To fix that take runtime get reference before MHI operations and
runtime put later.
Change-Id: Icef23910587ff280270bdd7c60ad8eba392822e9
CRs-Fixed: 3464127
Some platform PCIe RC impedance can't achieve the target defined in spec.
It will result to Genoa card link down. To WA the issue, downgrade RC speed
to Gen1 for auto Genoa EP. Because the linkdown issue may happen during
enum, and before enumunation we do not know EP device ID, so set init
speed to Gen1, and then restore speed to default for others wifi chip.
The change does not affect Genoa throughput, because Gen1 speed is enough
for Genoa.
Change-Id: Iffdbf8b98a82c200faf11edcdd180213366ed6ca
CRs-Fixed: 3479848
Add support for AUX UC download functionality if aux support is
indicated by both host and fw.
Change-Id: I3bfbebbb5cdfbbaa350a34378ab2f0809f27affb
CRs-Fixed: 3402104
MHI INIT called during host driver registration leads to MHI state
mismatch because MHI is already in INIT state due to power up of
device as part of ongoing self recovery.
To fix this issue, avoid powering up device during recovery if host
driver is not registered. Device would be powered up later during
host driver registration.
Change-Id: I534dfc0e389ba97a6e2c4869d42be5ecff9609b3
CRs-Fixed: 3476947
Read MSI-X address from device tree file and initialize
MSI-X address and data to support MSI-X interrupts.
Change-Id: I7cc43ca4d3e4c937f09facf12dd02437ddc2e039
CRs-Fixed: 3488821
API cnss_send_buffer_to_afcmem pass AFC data from driver to target
which is not changed in platform driver, and it is pass-through byte
stream for platform driver.
Change the AFC data pointer in API from char* to const uint8_t*.
Change-Id: Ib492dbcf028776858926d8a3e11edc528566fac1
CRs-Fixed: 3478093
Cnss2 driver receives cnss_pci_smmu_fault_handler cb from smmu
driver whenever wlan fw access illegal IOVA address. In
cnss smmmu fault cb handler, cnss2 driver rings trace stop
door bell register to stop tracing in wlan fw. This will
help to get proper traces to debug where illegal access
is happening in wlan fw.
Change-Id: I953ced55d4d847ccaabad15f5f70150aec8aabd6
CRs-Fixed: 3459443
Add one new device tree config item "qcom,sleep-clk-supported"
to support enable 32k internal sleep clock in case it has no
external 32k clk attached in wlan chipset HW. Like qca6390
on some auto platform, host need explicitly tell firmware
to use internal sleep clock, otherwise it will cause LMAC
ps failure.
Change-Id: I52f5d332a912235596eb127ab8e4660355988038
CRs-Fixed: 3448595
Add new "qcom,no-bwscale" under child device node to
indicate it want to disable bw scalling.
And the background is like HSP, it has stability issue
with some specific pcie cable with gen3, so it will
negotiate with RC side to change from gen3 to gen2
with MHI_ER_BW_SCALE_ELEMENT_TYPE event, which will
impact all the platform that want to keep use gen3.
So add this device tree config item to skip the link
speed negotiation.
Change-Id: I4a8d94a50dd740b84c3eeac435c5a19098b79ad9
CRs-Fixed: 3435289
Access to PBL and SBL log region in SRAM is restricted in
Mission mode. Avoid PBL/SBL log region dump in Mission mode.
Change-Id: Ia8813ccd9e2c0339c280e6cb6d6f0bab0bee206e
CRs-Fixed: 3432159
It costs 4M when loading cnss2, if device id is QCA6490 and enabled
CONFIG_CNSS2_DEBUG. Which is big memory consumption for low rate issue
debugging. So add CONFIG_DISABLE_CNSS_SRAM_DUMP to disable sram_dump.
Change-Id: Iacf338a3cc8f1583e16034a9873029a450fd254a
CRs-Fixed: 3441274
Currently genoa is using lower 32 bits of 64 bit dma
bitmask. Unexpected access of higher 32 bits may cause
issues.This code change avoids such possibilities.
Change-Id: I8bf17056a12661a7c50333bf5897721d363550a3
CRs-Fixed: 3428036
At the auto platform, DRV feature is not applicable.
So do not issue any DRV related operation from cnss2
side, which may cause the RC PHY not ready in the LPM
case.
Change-Id: Iefae9a885c1adc289da518d65a2974e127bdf359
CRs-Fixed: 3419811
Peach supports TME-Lite to validate FW image. TME-Lite supported
FW image format is different from currently used FW images and it
requires different way of downloading in MHI layer. Set TME-Lite
supported flag in MHI controller for Peach to inform MHI about
FW image format.
Change-Id: I615570914c9cec297aa422ce683b4d1c6c75ea1c
CRs-Fixed: 3364546
For whatever reason, the qca6390 is not in M3 state
during PM resume phase, but still functional if do
force resume. So calling mhi_pm_resume_force()
instead of the mhi_pm_resume() to unblock PM
resume for kernel 5.15.
Reference link:
https://lore.kernel.org/regressions/871r5p0x2u.fsf@codeaurora.org/
As for lower kernel version, like 5.4, it will do local
mhi pm state check in the mhi_pm_resume() instead of
target pm state check, so has no issue with qca6390.
Change-Id: I54c2cef457405720386af6a6f7d4617f3d081875
CRs-Fixed: 3402571
Should power off HST/HSP if it only finished pcie
enumeration without WLAN driver load before do
LPM. Otherwise, it will cause the mhi state switch
from INIT to SUSPEND failure that block LPM.
Change-Id: Ia2c5fbf0a2bf9c088be548eb533d7836f45a3cfd
CRs-Fixed: 3283893
Current implementation tries to collect FW dump when cnss shutdown,
and then ASSERT after collection complete.
Do not invoke CNSS_ASSERT if SSR enabled.
Change-Id: I8d427603bfc7e6bb5d732fa3e29ff66c965e153b
CRs-Fixed: 3399930
Add cnss2 code changes to register with thermal framework to support
thermal mitigation.
Change-Id: I9d427603bfc7e6bb5d732fa3e29ff66c965e153b
CRs-Fixed: 3386762
Currently, the cnss2 platform driver just can support
one wlan device attached, so do the following changes
to cover dual wlan card attach case. Firstly, delay
the second device go to pcie link suspend and power
off state to make sure it really finished the pcie
enumeration. Then pcie enumeration succeeds with
multi-devices. Secondly, supporting to write the qrtr
node instance id to PCIE register for wlan fw reading,
which can fix qmi message exchange failure if active
two Hastings devices. Thirdly, change the usage of
plat_env to support dual Hastings.
Change-Id: Ica41a23d4e983b91c0ff1b4e76b380803fb877ab
Call collect_driver_dump() driver ops to add the data from the buffer
for the four log types.
Change-Id: Ic06d4520de6f87202d1c3ce24362d61002b85f61
CRs-Fixed: 3352310
If device tree doesn't configure any regulators for
device, means this device doesn't need extra regulator.
This case shall not be treated as an error.
Return a positive value for this case to allow caller to
make proper choice.
Change-Id: I7ead81b3915d16f966f94c9d916e0d67bc04fda0
CRs-Fixed: 3355141
Some auto HW can't guarantee wlan_en low state when powerup.
Add a macro to enable initializing wlan_en state.
Change-Id: I6755bcd49c78f7bb9931f80cb385e62177ebe603
CRs-Fixed: 3355148
Added below mentioned changes to support qca6174 in cnss2 driver.
1. While resuming pci link, restore the pci config space before
enabling pci device.
2. Add 10ms delay between wlan_en become active and pcie reset
de-assert.
3. For wlan chipsets which don't support cold boot calibration,
schedule Wlan driver load in cnss_cold_boot_cal_start_hdlr.
Change-Id: I28435896314783353db5dd830051df9467be6585
CRs-Fixed: 3359223
Before CNSS2 triggers RDDM mode in device it collects shadow
register dump in a global variable. Now when device moves to
RDDM, shadow registers will be reset. Reading shadow registers
in RDDM mode will override previously read correct values with
reset values. To avoid it, do not dump shadow register in RDDM
mode.
Change-Id: I470208be7e38bc9291932a7acfbaf07d87d46651
Do not invoke the mhi_control_error to notify the pcie link down event
for QCA6174 to avoid NULL pointer access.
Change-Id: I2c899ab51117aef2f9474e83217229b211eb4759
CRs-Fixed: 3335555
Only when SMMU S1 enabled, CNSS driver will send IOVA range in
HOST_CAP message, and let firmware to configure ATU.
Change-Id: Idd19063da975c0105d91e0e31575d0b0d1edd8e2
CRs-Fixed: 2896035
Add APIs for handling AFC memory request from FW:
cnss_send_buffer_to_afcmem() and cnss_reset_afcmem().
cnss_send_buffer_to_afcmem() will be called if receive valid AFC
response data, cnss_reset_afcmem() will be called if receive
invalid AFC response data. After memory copy done, another WMI
command will indicate FW ready to read.
Change-Id: I34b9add3d7721d778e5474d9b11ad64adb4f04f0
CRs-Fixed: 3223607
This refine commit 418727f314 ("cnss2: Print the bandwidth level voted"),
to avoid too many vote log in dmesg during traffic test.
Change-Id: Ia260a84bcdb3e5154376471519340db1b5907ce4
CRs-Fixed: 3273973
CNSS2 registers as both platform and PCI driver. PCI
device can be removed via sysfs exposed by kernel during
PCI device creation. When PCI device gets removed, CNSS
PCI remove ops gets called. In cnss_pci_remove, unregister
host driver and shutdown WLAN chip to cleanly remove PCI
device.
Change-Id: Ia60e8b69bda2b3bdd5990cb83f47c082d6667283
CRs-Fixed: 3308910
The reservation mode of interrupts in kernel assigns a dummy vector
when the interrupt is allocated and assigns a real vector when the
request_irq is called. The reservation mode helps to ease vector
pressure when devices with a large amount of queues/interrupts
are initialized, but only a minimal subset of those queues/interrupts
is actually used.
So on reservation mode, the msi_data may change after request_irq
is called, so reads msi_data again after mhi request_irq is called,
and then the correct msi_data is programmed into hardware components.
Without this change, spurious interrupt occurs in case of one MSI
vector.
Change-Id: I41070987798835f8fa95304fce3b964bbd77b31d
CRs-Fixed: 3313984
Some platforms can't meet the number of MSI interrupt vectors that
wlan driver requires.
Add one MSI interrupt vector support.
If CONFIG_ONE_MSI_VECTOR is not defined, wlan driver fails to load
if reuired MSI vector allocation fails. It is current behavior.
If CONFIG_ONE_MSI_VECTOR is defined, firstly it will allocate multiple
MSI vectors based on MSI config. If MSI vector allocation fails, it
fallbacks to one MSI vector automatically.
Change-Id: I813f7ddf678ecf405e573f3bc72af3e758d1c96d
CRs-Fixed: 3312670
