cnss2: Skip any adsp operation if DRV not supported

At the auto platform, DRV feature is not applicable.
So do not issue any DRV related operation from cnss2
side, which may cause the RC PHY not ready in the LPM
case.

Change-Id: Iefae9a885c1adc289da518d65a2974e127bdf359
CRs-Fixed: 3419811

cnss2/pci.c

@@ -6359,7 +6359,7 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv)
 	}
 
 	/* MHI satellite driver only needs to connect when DRV is supported */
-	if (cnss_pci_is_drv_supported(pci_priv))
+	if (cnss_pci_get_drv_supported(pci_priv))
 		cnss_mhi_controller_set_base(pci_priv, bar_start);
 
 	/* BW scale CB needs to be set after registering MHI per requirement */
@@ -6748,6 +6748,9 @@ static int cnss_pci_probe(struct pci_dev *pci_dev,
 	if (ret)
 		goto unregister_ramdump;
 
+	/* update drv support flag */
+	cnss_pci_update_drv_supported(pci_priv);
+
 	ret = cnss_reg_pci_event(pci_priv);
 	if (ret) {
 		cnss_pr_err("Failed to register PCI event, err = %d\n", ret);

cnss2/pci_platform.h

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
+/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
 
 #ifndef _CNSS_PCI_PLATFORM_H
 #define _CNSS_PCI_PLATFORM_H
@@ -112,7 +112,8 @@ bool cnss_pci_is_one_msi(struct cnss_pci_data *pci_priv);
 int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv);
 bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv);
 int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv);
-bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv);
+void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv);
+
 /**
  * _cnss_pci_get_reg_dump() - Dump PCIe RC registers for debug
  * @pci_priv: driver PCI bus context pointer
@@ -198,12 +199,18 @@ int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
 	return 0;
 }
 
-bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
+void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv)
 {
-	return false;
+	pci_priv->drv_supported = false;
 }
+
 #endif /* CONFIG_PCI_MSM */
 
+static inline bool cnss_pci_get_drv_supported(struct cnss_pci_data *pci_priv)
+{
+	return pci_priv->drv_supported;
+}
+
 #if IS_ENABLED(CONFIG_ARCH_QCOM)
 int cnss_pci_of_reserved_mem_device_init(struct cnss_pci_data *pci_priv);
 int cnss_pci_wake_gpio_init(struct cnss_pci_data *pci_priv);

cnss2/pci_qcom.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
+/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
 
 #include "pci_platform.h"
 #include "debug.h"
@@ -159,7 +159,7 @@ static int cnss_pci_set_link_down(struct cnss_pci_data *pci_priv)
 	return ret;
 }
 
-bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
+void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv)
 {
 	struct pci_dev *root_port = pcie_find_root_port(pci_priv->pci_dev);
 	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
@@ -169,7 +169,7 @@ bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
 	if (!root_port) {
 		cnss_pr_err("PCIe DRV is not supported as root port is null\n");
 		pci_priv->drv_supported = false;
-		return drv_supported;
+		return;
 	}
 
 	root_of_node = root_port->dev.of_node;
@@ -189,8 +189,6 @@ bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
 		plat_priv->cap.cap_flag |= CNSS_HAS_DRV_SUPPORT;
 		cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
 	}
-
-	return drv_supported;
 }
 
 static void cnss_pci_event_cb(struct msm_pcie_notify *notify)
@@ -268,7 +266,7 @@ int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
 			    MSM_PCIE_EVENT_LINKDOWN |
 			    MSM_PCIE_EVENT_WAKEUP;
 
-	if (cnss_pci_is_drv_supported(pci_priv))
+	if (cnss_pci_get_drv_supported(pci_priv))
 		pci_event->events = pci_event->events |
 			MSM_PCIE_EVENT_DRV_CONNECT |
 			MSM_PCIE_EVENT_DRV_DISCONNECT;
@@ -299,6 +297,9 @@ int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
 	u32 pm_options = PM_OPTIONS_DEFAULT;
 	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
 
+	if (!cnss_pci_get_drv_supported(pci_priv))
+		return 0;
+
 	if (plat_priv->adsp_pc_enabled == control) {
 		cnss_pr_dbg("ADSP power collapse already %s\n",
 			    control ? "Enabled" : "Disabled");