cnss2: Add force one MSI field for quirk

Add new bit FORCE_ONE_MSI for quirk to force one MSI configure

Change-Id: I5053a0f95619ee75aad8a4c3f413affc0f9af3f5
CRs-Fixed: 3313980

cnss2/debug.c

@@ -816,6 +816,9 @@ static int cnss_show_quirks_state(struct seq_file *s,
 		case DISABLE_TIME_SYNC:
 			seq_puts(s, "DISABLE_TIME_SYNC");
 			continue;
+		case FORCE_ONE_MSI:
+			seq_puts(s, "FORCE_ONE_MSI");
+			continue;
 		default:
 			continue;
 		}

cnss2/main.h

@@ -370,6 +370,7 @@ enum cnss_debug_quirks {
 	DISABLE_IO_COHERENCY,
 	IGNORE_PCI_LINK_FAILURE,
 	DISABLE_TIME_SYNC,
+	FORCE_ONE_MSI,
 	QUIRK_MAX_VALUE
 };
 

cnss2/pci.c

@@ -4429,7 +4429,12 @@ static int cnss_pci_enable_msi(struct cnss_pci_data *pci_priv)
 	if (pci_priv->device_id == QCA6174_DEVICE_ID)
 		return 0;
 
-	ret = cnss_pci_get_msi_assignment(pci_priv);
+	if (cnss_pci_is_force_one_msi(pci_priv)) {
+		ret = cnss_pci_get_one_msi_assignment(pci_priv);
+		cnss_pr_dbg("force one msi\n");
+	} else {
+		ret = cnss_pci_get_msi_assignment(pci_priv);
+	}
 	if (ret) {
 		cnss_pr_err("Failed to get MSI assignment, err = %d\n", ret);
 		goto out;

cnss2/pci_platform.h

@@ -105,10 +105,12 @@ int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up);
 int cnss_pci_prevent_l1(struct device *dev);
 void cnss_pci_allow_l1(struct device *dev);
 int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv);
+int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv);
 bool cnss_pci_fallback_one_msi(struct cnss_pci_data *pci_priv,
 			       int *num_vectors);
 bool cnss_pci_is_one_msi(struct cnss_pci_data *pci_priv);
 int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv);
+bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv);
 int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv);
 bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv);
 /**

cnss2/pci_qcom.c

@@ -456,7 +456,7 @@ int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv)
 }
 
 #ifdef CONFIG_ONE_MSI_VECTOR
-static int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv)
+int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv)
 {
 	pci_priv->msi_config = &msi_config_one_msi;
 
@@ -499,7 +499,18 @@ int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv)
 	return MHI_IRQ_NUMBER;
 }
 
+bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv)
+{
+	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
+
+	return test_bit(FORCE_ONE_MSI, &plat_priv->ctrl_params.quirks);
+}
 #else
+int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv)
+{
+	return 0;
+}
+
 bool cnss_pci_fallback_one_msi(struct cnss_pci_data *pci_priv,
 			       int *num_vectors)
 {
@@ -515,6 +526,11 @@ int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv)
 {
 	return 0;
 }
+
+bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv)
+{
+	return false;
+}
 #endif
 
 static int cnss_pci_smmu_fault_handler(struct iommu_domain *domain,