Writeback cropping should only be enabled in concurrent writeback
usecases, and otherwise can lead to writeback failures. This change
adds a check for this before enabling the feature.
Change-Id: I587c1e755810c836fb64291ec3b0005bc28efdc2
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
With dedicated concurrent write back feature enabled, only one
cwb overflow irq is initialized. However, the table has not been
updated to reflect this. This can result in bad attempts to
register unavailable overflow irqs for different pingpongs.
This change creates a new dcwb irq table to be used when
dcwb is enabled.
Change-Id: Ib683b4cdaea2d2fe4f1131b92b1abaa096fa2cc0
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
The offset for DP pixel clock configuration registers in disp_cc has
changed in waipio. Currently the driver is using incorrect offsets to
read M/N values to calculate SW MVID/NVID during MSA programming. This
results in a blank screen as the sink is not able to restore the pixel
clock.
This change fixes this issue by selecting the correct base address
based on dp core version.
Change-Id: I44214ce52c1bc346715362df0a138f1f8cc011e1
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
This reverts commit 6886d03e4a.
It tries to memset the pstate from UI thread (crtc atomic check)
and crtc commit thread.
Change-Id: Ic9d3e5555d7085832df76025e53488d2b3365739
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
With the change in the clock names for newer targets, this fix
updates the driver to support different clock names per target.
Change-Id: I58c35fce34356f8c79adb0ac8a907e2fb60813ae
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Enable the vblank feature to report the precise HW vsync timestamp
using the DRM vblank timestamp and counter hooks for waipio target.
Change-Id: If4224e19572b8e08cb76296d11b7154fe9a16375
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signal the retire/release fences from within the sde driver instead of
calling the dma-fence api. This allows the driver to set the desired
timestamp for the fences. Replicate the dma-fence api functionality to
set the signaled and timestamp flags and handle the registered callbacks.
Change-Id: I951b599fc92d6d054847f24f0acb04aee27bdefb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Retire fence for frames are signaled based on vsync. Use the HW
vsync timestamp counter to calculate the precise vsync timestamp
and update the retire fence signal timestamp. This will offset
all IRQ and SW delays and sends the precise timestamp. Avoid
calculating the timestamp on error or panel dead events and
set the current ktime for those cases.
Change-Id: Ic762f7cd6daead9c8fdcb0f8aad6386cf980407d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add precise vblank timestamp support through the DRM framework.
Implement the vblank related hooks to get the vblank count and
timestamp. Use MDSS 8.x, hardware feature that supports logging
of the vsync timestamp counter which can be used to derive the
accurate kernel timestamp. The current ktime would be returned
for older targets to support backward compatibility.
Change-Id: I2d35ed4a643a519e602278b6d16e67ccee16a60b
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 8.x, vsync timestamp counter register is added in all the
interfaces. Add interface to get the vsync counter and use the global
qtmr reference counter to get the counter delta. This can be used
with reference to the curret ktime to deduce the accurate vsync
timestamp. This utility is intended to be used for setting the vblank
and retire fence timestamps which would be notified to user-mode.
Change-Id: I608a284c035cda50053eedbb311f1f54b3d3d557
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 8.x INTF line/frame counters can be reset through
a register. Reset these counters during timing engine enable /
tear-check enable to keep track of meaningful counters, which
would be useful during debugging. Additionally, reset the
counters during cont-splash modeset to track the number of
auto-refresh frames while disabling it during the first frame.
Change-Id: I66b45f5b29793df1fb4635972b1c614ad8c3b5b3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently the timing configuration for test pattern generator in DP
controller assumes that the widebus is disabled. This change adds the
check for widebus and adjusts timing configuration accordingly.
Change-Id: Id86601c910e88705a1a6d0ff4a4b38df6a843409
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Updating the link clock name in dp parser to account for
the changes made in the dtsi file.
Change-Id: Ic5c018a04b0e3dd3ac90387d76b5b0295323b144
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
On Waipio target, periph top0 block has been removed from mdp top
register block. This creates a hole in the accessible register space
and can lead to NOC errors. In addition, accessing register offset
for invalid dedicated concurrent write back can lead to NOC errors.
This change adds support for indicating if the periph block has been
removed and splitting the mdp top register block into two for reg dump.
In addition, it only registers valid dcwb to be reg dumped by
adding a dcwb count.
Change-Id: I23931cdf5ce4d858a3837f3946b54d9231e0db27
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This change exposes capabilities for CWB ROI to userspace
as well as implements the cropping feature which is now supported.
Change-Id: Idf76727175bf7c183367be715eaa45f3a432640c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
DPU has added support for noise injection into the layer stack. Change
adds support for noise layer programming and exposes the hardware block
to the user space modules.
Change-Id: Id176eea54fcdcd5d399457b14133a1ccde07299f
Noise layer feature is supported on certain version of dpu. Change adds
parsing support for the feature into the sde hw catalog.
Change-Id: I8037cab1d7bba1ea74c13c917ee5a36c50dc50cf
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Change rounds up the calculated byte clock rate to the nearest
even number.
Change-Id: Iea6d3121343f1b2cb6d0a06cd47a84b050d55ac1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change updates the pclk divider calculation to ensure
more accurate pclk rate for DSI.
Change-Id: Iaf3a5b6e4b10ac751b3a80e2c3041ab8260b21e5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For DPHY, DSI byte clock is used to derive the byte interface clock through
a DIV_2 divider. While setting the rate for byte interface clock, if the byte
clock rate is odd the recalculation of byte interface clock will fail. This
can further lead to recalculation of byte clock and result in unexpected
value for byte clock. The change ensures that for DPHY, the byte clock rate is
always even to avoid such issues.
Change-Id: I0a0371af75e5819ed1283b52b4681e70f55d66e0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Set the boolean property to enable dedicated
CWb feature on Waipio hardware.
Change-Id: I033691fd948729e7b6cef72a2d00c3ca2faedcae
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
For dedicated CWB pingpong blocks, the overflow irq needs
to be mapped properly to existing IRQ handlers. Add the
needed changes in code.
Change-Id: Ibf398faac60acc027e4577504f9292ac2b72bae2
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add dummy layer mixer blocks to be used for dedicated
CWB.
Change-Id: Ie1fe4fa7502cf5cf4dba3f2c129257887a20b7ad
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add new capture/tap point as CRTC property for
D-CWB feature. Update the hardware blocks and
corresponding APIs to configure D-CWB data path.
Add new hardware pingpong blocks that
are dedicated for CWB.
Change-Id: I22576df1768b50f9f47d8527f62913b01ff4d9a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Watchdog timer is moving from TOP to INTF. This change adds
support for movement and ensures backwards compatibility.
Vsync select only needs to specify whether or not to use
Timer 0 associated with the interface. It does not need to
select between Timer 0-4.
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change-Id: I9d89a8cb1ea607e9fc0bdbffa0a6a9acceff7f13
Remove edid/dpcd simulation function from dp_debug and calls to
sim bridge instead to simplify dp_debug module. Also add mst edid
support and mst hpd simulation from aux level.
Move selected mode from dp_debug module to dp_panel module to
simplify mst handling and decouple dp_debug from main dp driver.
Remove custom edid/dpcd mode from dp_panel and dp_aux module.
Remove mst connector list handling from dp_display module.
Change-Id: Ife1d2deb0e353f0a9695b7b90e5bf3459e1c81f7
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Karim Henain <khenain@codeaurora.org>
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
REG DMA programming occurs with respect to the sub-block top,
but all registers catalogued are with respect to sspp top.
This change adds support for handling the updated
sspp sub-block top and retains a default value for backward
compatibility.
Change-Id: I5a6364b17e817e38cd5afbcc67ed9df98c024008
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Introduce support for the FP16 format and FP16 color processing
blocks. This includes support for FP16, FP16 UBWC, and inline
rotation on tiled FP16 pixel data.
Change-Id: I06a70cab5447140598682f687129d4f8662524b2
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Kernel cannot guarantee the order in which DMA sub blocks (DGM blocks)
device tree entries are parsed. This could lead to misinterpreting
register offsets. This change adds support for reading the index
of the dgm node to correctly correspond with hardware.
Change-Id: If7ae7afc858089d95f81aea071dc32ddab334555
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
