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@@ -50,6 +50,9 @@
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#define MDP_WD_TIMER_4_CTL2 0x444
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#define MDP_WD_TIMER_4_LOAD_VALUE 0x448
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+#define MDP_PERIPH_TOP0 0x380
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+#define MDP_SSPP_TOP2 0x3A8
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+
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#define AUTOREFRESH_TEST_POINT 0x2
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#define TEST_MASK(id, tp) ((id << 4) | (tp << 1) | BIT(0))
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@@ -695,9 +698,21 @@ struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "mdss_hw", 0,
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m->mdss_hw_block_size, 0);
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- sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
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+ if (test_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &m->mdp[0].features)) {
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+ char name[SDE_HW_BLK_NAME_LEN];
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+
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+ snprintf(name, sizeof(name), "%s_1", cfg->name);
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+
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+ sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, mdp->hw.blk_off,
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+ mdp->hw.blk_off + MDP_PERIPH_TOP0, mdp->hw.xin_id);
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+
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+ sde_dbg_reg_register_dump_range(SDE_DBG_NAME, name, mdp->hw.blk_off + MDP_SSPP_TOP2,
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+ mdp->hw.blk_off + mdp->hw.length, mdp->hw.xin_id);
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+ } else {
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+ sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
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mdp->hw.blk_off, mdp->hw.blk_off + mdp->hw.length,
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mdp->hw.xin_id);
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+ }
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sde_dbg_set_sde_top_offset(mdp->hw.blk_off);
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return mdp;
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