disp: msm: dp: fix disp_cc offsets for pixel clk dividers

The offset for DP pixel clock configuration registers in disp_cc has
changed in waipio. Currently the driver is using incorrect offsets to
read M/N values to calculate SW MVID/NVID during MSA programming. This
results in a blank screen as the sink is not able to restore the pixel
clock.

This change fixes this issue by selecting the correct base address
based on dp core version.

Change-Id: I44214ce52c1bc346715362df0a138f1f8cc011e1
Signed-off-by: Sudarsan Ramesh <[email protected]>

msm/dp/dp_catalog.c

@@ -123,6 +123,7 @@ struct dp_catalog_private {
 	struct dp_catalog dp_catalog;
 
 	char exe_mode[SZ_4];
+	u32 dp_core_version;
 };
 
 static u32 dp_read_sw(struct dp_catalog_private *catalog,
@@ -1949,6 +1950,9 @@ u32 dp_catalog_get_dp_core_version(struct dp_catalog *dp_catalog)
 	}
 
 	catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
+	if (catalog->dp_core_version)
+		return catalog->dp_core_version;
+
 	io_data = catalog->io.dp_ahb;
 
 	return dp_read(DP_HW_VERSION);

msm/dp/dp_catalog_v420.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 
@@ -8,6 +8,15 @@
 #include "dp_reg.h"
 #include "dp_debug.h"
 
+#define MMSS_DP_PIXEL_BASE_V130			(0x1A8)
+#define MMSS_DP_PIXEL1_BASE_V130		(0x1C0)
+
+#define MMSS_DP_PIXEL_BASE_V140			(0x1BC)
+#define MMSS_DP_PIXEL1_BASE_V140		(0x1D4)
+
+#define MMSS_DP_M_OFF				(0x8)
+#define MMSS_DP_N_OFF				(0xC)
+
 #define dp_catalog_get_priv_v420(x) ({ \
 	struct dp_catalog *catalog; \
 	catalog = container_of(x, struct dp_catalog, x); \
@@ -146,8 +155,10 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
 	u32 const nvid_fixed = 0x8000;
 	u32 const link_rate_hbr2 = 540000;
 	u32 const link_rate_hbr3 = 810000;
+	struct dp_catalog *dp_catalog;
 	struct dp_catalog_private_v420 *catalog;
 	struct dp_io_data *io_data;
+	u32 version;
 
 	if (!panel || !rate) {
 		DP_ERR("invalid input\n");
@@ -159,14 +170,27 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
 		return;
 	}
 
-	catalog = dp_catalog_get_priv_v420(panel);
+	dp_catalog = container_of(panel, struct dp_catalog, panel);
+	catalog = container_of(dp_catalog->sub, struct dp_catalog_private_v420, sub);
+
+	version = dp_catalog_get_dp_core_version(dp_catalog);
 	io_data = catalog->io->dp_mmss_cc;
 
-	if (panel->stream_id == DP_STREAM_1)
-		reg_off = MMSS_DP_PIXEL1_M_V420 - MMSS_DP_PIXEL_M_V420;
+	if (version >= 0x10040000) {
+		if (panel->stream_id == DP_STREAM_1)
+			reg_off = MMSS_DP_PIXEL1_BASE_V140;
+		else
+			reg_off = MMSS_DP_PIXEL_BASE_V140;
+	} else {
+		if (panel->stream_id == DP_STREAM_1)
+			reg_off = MMSS_DP_PIXEL1_BASE_V130;
+		else
+			reg_off = MMSS_DP_PIXEL_BASE_V130;
+	}
+
 
-	pixel_m = dp_read(MMSS_DP_PIXEL_M_V420 + reg_off);
-	pixel_n = dp_read(MMSS_DP_PIXEL_N_V420 + reg_off);
+	pixel_m = dp_read(reg_off + MMSS_DP_M_OFF);
+	pixel_n = dp_read(reg_off + MMSS_DP_N_OFF);
 	DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
 
 	mvid = (pixel_m & 0xFFFF) * 5;

msm/dp/dp_reg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _DP_REG_H_
@@ -398,10 +398,6 @@
 #define MMSS_DP_PIXEL_N_V200			(0x0134)
 #define MMSS_DP_PIXEL1_M_V200			(0x0148)
 #define MMSS_DP_PIXEL1_N_V200			(0x014C)
-#define MMSS_DP_PIXEL_M_V420			(0x01B0)
-#define MMSS_DP_PIXEL_N_V420			(0x01B4)
-#define MMSS_DP_PIXEL1_M_V420			(0x01C8)
-#define MMSS_DP_PIXEL1_N_V420			(0x01CC)
 
 /* DP HDCP 1.3 registers */
 #define DP_HDCP_CTRL                                   (0x0A0)