513385718470bd5832dc286fdc7ec9161c739830

The offset for DP pixel clock configuration registers in disp_cc has changed in waipio. Currently the driver is using incorrect offsets to read M/N values to calculate SW MVID/NVID during MSA programming. This results in a blank screen as the sink is not able to restore the pixel clock. This change fixes this issue by selecting the correct base address based on dp core version. Change-Id: I44214ce52c1bc346715362df0a138f1f8cc011e1 Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
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