Check and update register sequences for wcd9395 version
2.0.
Change-Id: I85fc739744ee2ba2c5dbdc853eb639b84cac6478
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
enable l_det_en bit while detecting the HS.
Issue: While removing HS some additional electrical interrupts
are triggered and reporting different events to userspace, which is
cause issues. To avoid this electrical interrupt flow, there is
a check in adc_hs_rem_irq for wcd_swch_level_remove() to check
for l_det_en bit status. Depends on this it will return from the
adc_hs_rem_irq() without going further.
Solution: Enabling the l_det_en bit will helps to avoid serving
electrical interrupt flow to further in adc_hs_rem_irq().So this
will helps to stop reporting different/unwanted events to user space.
Change-Id: I29d72b65ebb59969b69f3f8c7f4c7eb2debb0f1c
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
dma_vmap is not freed in else case of is_iova, so kfree dma_vmap
when is_iova is false. And also if dma_buf_vmap kernel map is
failed, need to end cpu access dma buf.
Change-Id: I111fb7a2a367a8418f46a7b5fc1459d135d7115e
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
During some concurrencies even though we are not
enabling the swrm port, we are trying to disable it.
which causes problem w.r.t clock disablement,
To avoid that we are updating the set bit only
when port is enabled, based on that bit we are taking
decision to disable or enable the port.
Change-Id: I6707c56c40dd3716917edc097c4b7bcad68261fd
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
During swr disconnect port, swr master num port is
updated based on the portinfo we receive from slave.
Instead update the master num port based on the ports
enabled. and also if requested port is not enabled
continue to check for other enable port instead of
returning error.
Change-Id: Ia8a6e4935df443f9833e01d56195b590afe3bb4a
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Add scale and alpha register value updates based
on computed digital xtalk cancellation gain.
Change-Id: I8c12e2ba7c1566476741fec5459a74549f19cf5f
Signed-off-by: Sam Rainey <quic_rainey@quicinc.com>
Update wcd939x-usbss mode on PA enable and disable.
Change-Id: I73a19ea73102ced5c8011a5a1567ebfa372b2e44
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
usbc USCI event gets called and removal is reported, where bit
0 of mbhc->intr_status i.e. (WCD_MBHC_ELEC_HS_INS) will be set to 0.
So in adc_hs_ins_irq() we can check if the WCD_MBHC_ELEC_HS_INS bit
is 0 or not, if 0 we just ignore the and return.
Change-Id: I5a7753a077f53c5cd26c8ad199899ff9c81ef7b8
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
During stress testing, observed master num port is
going out of bounds which is impacting the next usecase
and leads to bus clsh error.
added a check to set master num port to 0 if it is
going out of boundary.
Change-Id: If273230fcef612bae484b19c5b69506606b0e911
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
enable the wsa and wsa2 clk as per sequence.
Change-Id: Ieefa4b6ea7aec535d940d780b0ed923483b4d3ee
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Add support for modules to be built with Bazel for pineapple and kalama.
Create generic module registering system for multiple targets.
Change-Id: Ib92e4e6b8eaf022d9ba4f66f149c14228238ae21
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Remove all references to members of regmap struct,
which caused a dependency to the internal.h header
in regmap. Removing these references allows us to
remove the dependency on that header entirely. The
data in question have been replaced with defined
constants.
Change-Id: I6d302a4f2614dd094dd24a850360b4e12868ed88
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Remove drivers/clk/qcom/common.h, which is an
internal header that is unused in audio-ext-clk-up.c.
Change-Id: I62dbdfd87c717ec60461a32505cba1b603c5e512
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
When target enters into secure mode, HLOS receives an event to
place vote against sleep until writing of required registers
from TZ. Once the secure DMA registers write done, HLOS will
get a event to unvote against sleep.
Issue scenario: When device enter secure mode votes for sleep
against, before unvote event receives for TZ SSR is triggered.
When SSR triggers all votes are reset on ADSP. While recovering
from SSR, HLOS receives unvote event to HLOS, which will unvoting
of other use case vote and leading to NOC issue.
Solution: Maintain a counter for sleep against vote to
track the votes and unvotes. Also reset the sleep counter
if SSR is trigger as ADSP will reset all votes on SSR.
Change-Id: Ib1689d8f54408a9a80a12fb2697ba5c3d7087b9a
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Harmonium supports full and half rate modes for DAC.
Update DAC rate to swr clkdiv2 to achieve better
power performance.
Change-Id: I136a064dc258ee839ea78c9f1051ba34521ac871
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
Get the wcd939x power mode of from mixer ctls and configure
same power mode to wcd-usbss.
Change-Id: I9dc8fe586f7e7608da542b0986bb7c605fc552d4
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
