Color features are disabled during encoder disable, but reg dma
flush is not triggered. This change does reg dma flush for the
features to be disabled during encoder disable.
Change-Id: Ia74d4c43ad7b699f0097b49d86ad59529c0b3230
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Add changes to update the register_dump_range offset_start and
offset_end validation introduced as part of 'commit cfc54d3f22
("disp: msm: sde: add check to avoid registering invalid ranges in dump")'.
Change-Id: I5e4332687b37d7926afdce6903d8fea6ce2874b1
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Move DP disconnect process to DP work queue to fix DP
notification issue when disconnecting USB cable.
Change-Id: Ib864563f35012ae4499ca5e3002eb52d1084ae58
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
During Link CTS test, it is possible that the TE would trigger an HPD
IRQ right after LT. Currently we are waiting for a fixed delay before
sending connect notification to usermode, so that the driver can
process any attention work queue requests immediately. This change
checks for any pending attention work queue requests before waiting
for timeout. After the attention work is done with any test request,
TE can trigger an unplug before running the next test case. In the
current flow we send HPD notification at the end of the attention
work without checking the HPD status, leading to delay in processing
the test requests. Rectified here.
Change-Id: I600c69abfc31deee25e09756c73592854e3faa3b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change avoids the enabling or disabling of vblank for
virtual displays. It ensures that vblank remains disabled
regardless of userspace requests.
Change-Id: I104cae9b8c0c4770b5092df49bd30501b09cbbc7
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Update max value for brightness property during property install.
In dual display with different max brightness level, property install
happens for primary display with its max value. When there is brightness
update for secondary display then it will fail in check for set property
due comaparison with max brightness of primary display. Avoid this by
updating max value of brightness property to 0xFFFF.
Change-Id: Icb6f19312075670f228d371b15a1a81dffaab341
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Some panels need at least one frame to be transferred to GRAM
before enabling the backlight. This is done by delaying the
backlight update to these panels until the first frame commit
is completed. This feature is activated by setting the
"qcom,bl-update-flag = delay_until_first_frame" property in the
device tree. However, this feature adds delay in the POMS
(video 2 command) use case adversely. To address this additional
delay, avoid delaying the backlight for the POMS use case.
Change-Id: Ia25afd35f9fe4ffa7d56bddad2f0975a77f39fdf
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In trusted vm, a stub function is used for the panel_ops.bl_register,
hence the backlight_device bl->raw_bd used for WLED backlight type
remains uninitialized.
If the panel backlight is WLED, this can cause a NULL pointer
dereference in TVM during dsi_panel_bl_handoff().
Add a check before dereferencing bl->raw_bd.
Change-Id: Ieb40781263b4318313fd29b339122ae6c59b1590
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Add property to parse the ddr type and select the vbif QOS
values based on the detected ddr type.
Change-Id: Ifc980b5bdadc38b7b0882568a1f07e4e8441303a
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
Ensure to allocate switch type as bypass in case of dp aux switch
node missing in device tree entry and prevent any scope of null
pointer dereferencing.
Change-Id: I1d50d785e028f2e69a0effaedb2dbb6568a473dd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change fixes the 'commit 92cbd6d654 ("disp: msm: sde: while
timing engine enabling poll for active region")' which introduces
one frame time delay during enabling the timing engine.
Change-Id: Ibe71eb785822381fd23e74f4d55dbd141024d520
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Add changes to support odd number of dedicated-CWB.
Change-Id: I21c8521e98f6a8b5bb002f1c056afc501e7e9780
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
When enable spr 2d filer in PU case, The extra line will be over
fetch on top of roi. But for demura, it does not require over fetch.
Theresfore the height of demura plane is not same with the height
of LM.
Change modify the checking on height while set demura config.
Change-Id: Ie2232e0cd6ea0bec366a1f44b556cc13502cb512
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
In Commit N, llcc is enabled. However in Commit N+1, suspend
is triggered without a llcc disable commit. As a result, llcc
remains active, preventing ADSP from entering the island.
Change-Id: I36fd8cc8c3f8a97e18b53507749a1b639f0c0cfd
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
In the primary topology (2 2 1), during a full layer mixer
update, CWB requires two layer mixers. However, in the
scenario where Commit N has CWB enabled and uses two LMs
(Merge3D), and Commit N+1 has a single LM with partial update
Merge3D and two CWB and Merge 3D is programmed leads to commit
failure. This change addresses the issue by clearing the
existing configuration.
Change-Id: I8855d761c6eb6ad8809d94872ee961c6a721c541
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During VTS testing, simulated multi-frame delays
are set using the EPT (Expected Present Time)
property. The test case failed at lower refresh
rates. This change extendes the EPT timeout threshold
to 10 seconds, ensuring support for multiple frame
delays.
Change-Id: I75ee2f3b27083014e560c5819ed9929a137ef8da
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change add support for virtual sde blocks to maintain
the layer mixer id which is used for proper allocation of
dcwb.
Change-Id: I2b21561f72dab3ef833de71ceb1fa6dac886dc04
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
The issue scenario is as follows:
1. User space issues CWB commit N-1, frame got picked up and wr_ptr_irq
is received.
2. Next commit N CWB disable commit is programmed waits for N-1 wb_done
irq.
3. The kickoff count is decremented on wb_done_irq of commit N-1
and wb wait_for_idle is exited.
4. wb_frame_done irq thread execution stalled before populating fences
and commit thread execution continues.
5. wb_reset disables in_clone_mode flag, the stalled wb_done_irq thread
resumes its execution and signals the release fences on primary
CRTC.
6. Commit N-1 frame_done irq is received and release fences is
signaled again.
Userspace assumes Commit N also completed on receiving of second release
fence causing corruption in screen. This patch stores in_clone_mode
flag in wb_done_irq and only CWB retire fence is signaled.
Change-Id: I758e19178e4ba8722a01fca72d230f066831aec9
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This changes add checks to make sure LTM init is set
before setting VLUT.
Change-Id: Ifeeeb1ff176b2c91a2c5f43928fb9621b69585f0
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
This change enables the uidle feature support for palawan target.
Change-Id: I91010e4ce26dd74ea0e9367b6eee0165ee7814f7
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Destination scaler hw can be enabled and disabled runtime for
sharpness only case through QDCM.
Customer is using shared DSI solution and issue scenario is:
1) DS0 configured and enabled for INTF1 display1.
2) Suspend commit is triggered with DS0 disable configuration but
driver programming doesn't happen as crtc is not enabled.
for customer case, GDSC is not turned off due to extra vote.
3) On resume commit on INTF1 display2 with different resolution,
DS0 is not configured from userspace, but in HW,
DS0 programming is retained.
4) Due to this retained programming, DSI underflow is seen in
resume commit.
Add changes to disable dest scaler qseed opmode and merge ctrl
as part of cp crtc disable sequence.
Change-Id: Ibb39814e02870394da4c7c7318e6e2780fed9081
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL
registers to only while turning on the PLL.
Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
