Sixzonev2 uses a combination of broadcast enabled and disabled
cases to program luts and modify PA config registers respectively.
It also uses SB LUTDMA which requires all DSPP sub blocks to be
flushed. The modify operation can't be used with broadcast enabled and
was resetting the sub blocks to only indicate DSPP1 and causing the
DSPP_SB flush to be missed for DSPP 0. This change maintains the original
dspp indices to be used for broadcast enabled case and SB LUTDMA kickoff.
Change-Id: I1079878bbf44238419d4f88a40814e488c0800e3
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Suppose there's a mode change in Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.
Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.
Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In some corner cases there is pending vsync timestamp event to
sf when encoder is getting disabled. This is keeping vblank irq
to be enabled after sde_encoder_virt_reset leading to NULL ptr
access. In these cases, wait for vsync event to be completed which
disables the irq.
Change-Id: If0a6be1fc282906fb1b9c0fd18ede1d31d2549b3
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Change swaps right mixer flag when swapping mixer.
Histogram IRQ is registered to unexpected mixer
index if both mixers' right mixer flag set as false.
Change-Id: I0243d70129dc0c3bff24cabc8877c626101acd83
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
RSC Solver enable during autorefresh enable need to be avoided.
Currently in SDE driver, solver is disabled if autorefresh is
enabled from HLOS client but autorefresh disable transition is not
considered. This change avoids RSC solver mode in autorefresh
disable transition commit including splash hand-off.
Change-Id: Ib1c4791b203892629abdd84999671830a61f6ed0
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
In the case of DSI underflow or overflow, skip enabling back the DSI error
interrupts and instead send panel_dead. The error interrupt will be enabled
later by HAL as part of handling panel_dead event. Not enabling back the
DSI error interrupts immediately can prevent IRQ storm from occurring.
Change-Id: I769872bb5ac9ef8826c3e4caaab7723901dfc7d8
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Provide spr_roi region for spr over fetch in partial update.
Support different the roi size of connector and crtc.
Change-Id: Ic78a20badcafefd353a97532281dae26e5a772de
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
In current SDE driver, DSC resource allocation is done in
reverse order for DP displays. If this DSC resource allocation
invoked with array previously chosen DSC blocks, dereferencing
the array should be in same order of resource allocation to
avoid index mismatch and resource allocation failure.
Change-Id: I83fb74e6677effcf6ddaeea45a0bd6140fd1e6d5
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Adds a check for payload's vc_start_slot before attempting to finish
payload allocation. vc_start_slot is set to -1 on payload allocation
part 1 failure.
Prevents calling mst helper function on failed payload allocation.
Change-Id: I435f370616afbc875bffd9207b2eb1cf98086178
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
When HDCP enabled sink reports a link failure, it should
be a warning instead of an error because it can be part
of expected behavior during encryption level changes as
per spec. Also now prints debug statement on min enc
level changes.
Change-Id: I747f6997c32cfcdff9a4b6ca7e4750a651491833
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Sporadic link training failures occur when panel doesn't
respond to updating of link parameters.
Re-initialize panel after a link training failure when
the link rate is downshifted. Fixes sporadic lt failures.
Change-Id: I638996b9e7f478170aa4314c601772efd66edd16
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
During display disable, ensure source pipes are detached
from control path in the disable commit itself. Otherwise,
if other display acquire these pipes immediately it can hang
as these pipes are still staged on current display ctl path.
Change-Id: Idc376051908676c74bc26394372a92316a674e3b
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Adds null check for MST port and connector after payload
allocation. Prevents calling mst helper functions with
a null port or connector on a failed payload allocation.
Change-Id: I8e228bd1498b11b302371c1ad6d805d5f941667e
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Postpone virtual encoder reset until commit done complete
on all the encoders of the crtc to ensure cwb encoder
resources are held until it's primary encoder commit with
cwb resources disable is picked by HW.
Change-Id: I820317d13c00b44f6edd69acff83dc3b494b6282
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
calls
Replace direct modifications to vma->vm_flags with calls to modifier
functions to be able to track flag changes and to keep vma locking
correctness.
Change-Id: I4ad265028dc138912210eb907a7b0656c72b1464
Signed-off-by: jianzhou <quic_jianzhou@quicinc.com>
Passing the same error code received from the input fence error.
Change-Id: I59865e89eb974d1ee9f7c2fe3e13acd66cb82617
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add support for all the configs symbols under config_options under DDK framework.
Change-Id: Iba2949175afe5f55a2e3107d2afd71e55b862d61
Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com>
This change decrements the specific drm connector's reference count
after it has been used for reading crc frame value. Without this
change, there might be a chance of a connector's reference count
still remaining positive, even if it is not accessed anywhere
further in code.
Change-Id: I9058ca046fa114bc10159045f98c40ac68ade751
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change limits reglog feature by default to user debug
builds only and provides debug option to selectively disable
reglog for power and perf profiling if required. This change
is needed as reglog is considerably heavy on commit thread
execution.
Change-Id: Id06a63e10fd0c93ba0af6c6f2d1ae36b70c47f67
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
For MST Simulation use case, whenever the port status is updated on
an individual display, send a hotplug event to usermode to make
sure it is handled.
Change-Id: I959290f2c67378e057933356f3ffe692f8b858d7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
