Commit Graph

14 Commits

Author SHA1 Message Date
Vangala, Amarnath
443ca7a00e soc: swr-mstr: add support for bt swr ports
Add support for BT Soundwire port configurations.
Add support for flow control modes for fractional channel rates.
Configure slave side data ports for flow controls modes.
Fix the direction adn offset1 fields for Tx ports on BT Soundwire.
When the flow control mode is not required,
 update the slave configuration accordingly.
Sample Interval HIGH field in slave port controls needs to be
reset to zero when Sample Interval value is less than 255.
Avoid clock stop mode for bt swr slave during runtime suspend call.
In case of fractional sampling rates, additional offset bits need
 to be added between samples to carry flow control information.

Change-Id: If023946f62c5157119836cf43e8542cfd6e0ce16
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
2024-03-14 00:31:39 +05:30
Sarath Varma Ganapathiraju
b58f10f76f soc: add support for swr version 1p7
-add support for swr version 1p7.
-Return 0 instead of EBUSY during swrm_suspend to
allow system to enter suspend without rx swrm
preventing it.
- Update proper reg value during pcm port config.

Change-Id: Id42d3625a0609507fffc92b650cfae92b0e1dc4f
Signed-off-by: Sarath Varma Ganapathiraju <quic_ganavarm@quicinc.com>
2024-03-08 04:03:52 -08:00
Soumya Managoli
a5dda29cfd soc: swr-mstr-ctrl: Update SWR V1.6 registers
Update swr ver 1.6 registers.

Change-Id: I074a22305915b2ca38b6d6107fa253a435f92214
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
2022-08-12 20:02:32 +05:30
Matthew Rice
b51b1435d6 soc: Fix SWRM DIN Addresses and CPS offset1
SWRM_DIN_DP_* registers are based on incorrect register values.
Update to match correct hardware addresses.
Also fix tabs/spaces mismatch in same file.
Fix CPS offset1 port parameter to be 0 instead of 0xff.

Change-Id: I641a925f1f3b454a6af0d2491d86459131bba2cf
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
2022-05-12 14:43:58 -07:00
Matthew Rice
8f819a5cda soc: Fix bugs found in register updates to SWRM
Add CPU_m calculation in CPU_SW_MESSAGE.
Fix CLK_CTRL value. Skip 0x2C54 to 0x4000 in reg_show.

Change-Id: I487bfab9c9fa6c1e99af1b778da7d150ef5ac927
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
2022-01-20 21:29:57 -08:00
Meng Wang
787d1e3f92 soc: swr-mstr-ctrl: update correct mask for FIFO overflow/underflow
Update correct register mask for FIFO overflow/underflow
to avoid any potential issue.

Change-Id: Ie6220b1f653d1ec76ecc48a3dfa73aea39608e55
Signed-off-by: Meng Wang <quic_mengw@quicinc.com>
2021-12-07 09:53:17 -08:00
Matthew Rice
cb9ebaa0b7 soc: Initial Register Updates for SWRM2p0
Change-Id: If4bc240017cbec8c536ecfbbdb327231caa037da
Signed-off-by: Matthew Rice <mrice@quicinc.com>
2021-11-09 15:32:53 -08:00
Laxminath Kasam
1162b303cf soc: soundwire: Update interrupt masks based for CPU1 bits
In soundwire v1p7, CPU1 register bits used from Apps EE.
Update interrupt status and mask bits for CPU1 also to
be included.

Change-Id: Ied86e11756db8609fcd5b81e505f07a4c066c2b8
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2021-04-26 22:09:43 -07:00
Sudheer Papothi
1781f00ccc soc: soundwire: Update registers for multi execution environment
Update register definition for soundwire multi execution enviroment
to keep soundwire peripheral devices in clock stop mode when not
in use.

Change-Id: I3615d0dc7381df414b1fb9414d24cef921883668
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2021-02-17 06:25:18 +05:30
Laxminath Kasam
2489ca529c soc: swr-mstr-ctrl: Update multi_EE setting for clock_stop
Update link_manager and multi_EE clock stop settings
during master_init and clock stop wakeup.

Change-Id: Idc1610551304209c2688486b1061452ee4e2e46a
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-12-03 22:57:08 -08:00
Laxminath Kasam
98799c5e2f soc: soundwire: Update auto enum value from HW
remove macro for supported auto_enum slaves and
read from master comp_params. Update num_dev logic
to compare with supported auto enum slaves.

Change-Id: Iedadde5a3ee83645c4d8d16e738376e1797fc649
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-12-03 22:56:59 -08:00
Laxminath Kasam
38adb70f3c soc: swr-mstr: Update default val of comp_cfg
for PCM_OUT/IN dataport, update enable bit logic
using default value based on SWR version.

Change-Id: Ibfd342d9046834d074a12003f15e868c5336798c
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-12-03 22:56:31 -08:00
Vatsal Bucha
47b3116ec1 soc: swr-mstr: Avoid overflow during swr fifo read/write
Avoid swr fifo overflow by checking no. of outstanding
commands in fifo and comparing with fifo depth before
every read/write. If no. of commands is equal to fifo
depth then give some delay and retry. If no of outstanding
commands are still equal to fifo depth then flush fifo
and try writing/reading from fifo again.

Change-Id: Ifd986c7affb70a61f8a90e4960a2779273a7d4d2
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2020-07-22 21:53:18 -07:00
Sudheer Papothi
9d6350f7f0 soc: swr: update soundwire master and slave registers
Update soundwire master and slave registers based on the hardware
version.

Change-Id: I8a27bdfbbff133569a7391af8adddadd804bd50f
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2019-12-27 11:14:40 -08:00