soc: swr-mstr-ctrl: update correct mask for FIFO overflow/underflow

Update correct register mask for FIFO overflow/underflow
to avoid any potential issue.

Change-Id: Ie6220b1f653d1ec76ecc48a3dfa73aea39608e55
Signed-off-by: Meng Wang <[email protected]>

soc/swr-mstr-registers.h

@@ -62,8 +62,8 @@
 #define SWRM_CMD_FIFO_STATUS                 SWRM_CPU1_CMD_FIFO_STATUS
 #define SWRM_CMD_FIFO_RD_FIFO                SWRM_CPU1_CMD_FIFO_RD_FIFO
 #define SWRM_INTERRUPT_STATUS_MASK 				0x1DFDFD
-#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x200000
-#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x400000
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x40000
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x80000
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x100000
 #define SWRM_INTERRUPT_MAX					0x20
 #else