soc: soundwire: Update interrupt masks based for CPU1 bits

In soundwire v1p7, CPU1 register bits used from Apps EE.
Update interrupt status and mask bits for CPU1 also to
be included.

Change-Id: Ied86e11756db8609fcd5b81e505f07a4c066c2b8
Signed-off-by: Laxminath Kasam <[email protected]>

soc/swr-mstr-ctrl.c

@@ -51,7 +51,6 @@
 
 #define ERR_AUTO_SUSPEND_TIMER_VAL 0x1
 
-#define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
 #define SWRM_LINK_STATUS_RETRY_CNT 100
 
 #define SWRM_ROW_48    48
@@ -3099,7 +3098,7 @@ static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
 	u32 val;
 
 	dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
-	swr_master_write(swrm, SWRM_INTERRUPT_EN, 0x1FDFD);
+	swr_master_write(swrm, SWRM_INTERRUPT_EN, SWRM_INTERRUPT_STATUS_MASK);
 	val = swr_master_read(swrm, SWRM_MCP_CFG);
 	val |= 0x02;
 	swr_master_write(swrm, SWRM_MCP_CFG, val);

soc/swr-mstr-registers.h

@@ -38,6 +38,11 @@
 #define SWRM_CMD_FIFO_RD_CMD                 SWRM_CPU1_CMD_FIFO_RD_CMD
 #define SWRM_CMD_FIFO_STATUS                 SWRM_CPU1_CMD_FIFO_STATUS
 #define SWRM_CMD_FIFO_RD_FIFO                SWRM_CPU1_CMD_FIFO_RD_FIFO
+#define SWRM_INTERRUPT_STATUS_MASK 				0x1DFDFD
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x200000
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x400000
+#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x100000
+#define SWRM_INTERRUPT_MAX					0x20
 #else
 #define SWRM_INTERRUPT_EN                         (SWRM_BASE+0x0204)
 #define SWRM_INTERRUPT_EN_1                       (SWRM_BASE+0x0224)
@@ -45,6 +50,11 @@
 #define SWRM_CMD_FIFO_RD_CMD                      (SWRM_BASE+0x0304)
 #define SWRM_CMD_FIFO_STATUS                      (SWRM_BASE+0x030C)
 #define SWRM_CMD_FIFO_RD_FIFO                     (SWRM_BASE+0x0318)
+#define SWRM_INTERRUPT_STATUS_MASK 				0x1FDFD
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
+#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
+#define SWRM_INTERRUPT_MAX					0x11
 #endif /* CONFIG_SWRM_VER_1P7 */
 
 #define SWRM_CMD_FIFO_CMD                         (SWRM_BASE+0x0308)
@@ -95,13 +105,10 @@
 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                0x2
 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          0x4
 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  0x8
-#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
-#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              0x40
 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         0x80
 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               0x100
 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         0x200
-#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
 
 #ifdef CONFIG_SWRM_VER_1P1
 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED   0x800
@@ -120,8 +127,6 @@
 
 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP            0x10000
 
-#define SWRM_INTERRUPT_MAX    0x11
-
 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH		0x00007C00
 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH		0x000F8000