soc: Fix SWRM DIN Addresses and CPS offset1

SWRM_DIN_DP_* registers are based on incorrect register values.
Update to match correct hardware addresses.
Also fix tabs/spaces mismatch in same file.
Fix CPS offset1 port parameter to be 0 instead of 0xff.

Change-Id: I641a925f1f3b454a6af0d2491d86459131bba2cf
Signed-off-by: Matthew Rice <[email protected]>

asoc/kalama-port-config.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _KALAMA_PORT_CONFIG
@@ -29,7 +29,7 @@ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
 	{15,   6,    0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
 	{15,   13,   0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
 	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
-	{799,  0xFF, 0xFF, 15,   15,   24,   0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
+	{799,  0,    0xFF, 15,   15,   24,   0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
 };
 
 static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {

soc/swr-mstr-registers.h

@@ -35,11 +35,12 @@
 #define SWRM_LINK_STATUS(n)               (SWRM_BASE+0x4064+0x1000*n)
 #define SWRM_TO_CPU_SW_MESSAGE(n, m)      (SWRM_BASE+0x4090+0x1000*n+0x4*m)
 #define SWRM_TO_CPU_SW_MESSAGE_READ(n, m) (SWRM_BASE+0x40A0+0x1000*n+0x4*m)
+#define SWRM_DOUT_DP_FIFO_WATERMARK_CTRL(n) (SWRM_BASE+0x1060+0x100*n)
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
-#define SWRM_INTERRUPT_STATUS_MASK				0x1DFDFD
-#define SWRM_INTERRUPT_MAX					0x17
+#define SWRM_INTERRUPT_STATUS_MASK                              0x1DFDFD
+#define SWRM_INTERRUPT_MAX                                      0x17
 
 #else
 #define SWRM_INTERRUPT_STATUS                     (SWRM_BASE+0x0200)
@@ -62,11 +63,11 @@
 #define SWRM_CMD_FIFO_RD_CMD                 SWRM_CPU1_CMD_FIFO_RD_CMD
 #define SWRM_CMD_FIFO_STATUS                 SWRM_CPU1_CMD_FIFO_STATUS
 #define SWRM_CMD_FIFO_RD_FIFO                SWRM_CPU1_CMD_FIFO_RD_FIFO
-#define SWRM_INTERRUPT_STATUS_MASK 				0x1DFDFD
+#define SWRM_INTERRUPT_STATUS_MASK                              0x1DFDFD
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x40000
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x80000
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x100000
-#define SWRM_INTERRUPT_MAX					0x20
+#define SWRM_INTERRUPT_MAX                                      0x20
 #else
 #define SWRM_INTERRUPT_EN                         (SWRM_BASE+0x0204)
 #define SWRM_INTERRUPT_EN_1                       (SWRM_BASE+0x0224)
@@ -74,11 +75,11 @@
 #define SWRM_CMD_FIFO_RD_CMD                      (SWRM_BASE+0x0304)
 #define SWRM_CMD_FIFO_STATUS                      (SWRM_BASE+0x030C)
 #define SWRM_CMD_FIFO_RD_FIFO                     (SWRM_BASE+0x0318)
-#define SWRM_INTERRUPT_STATUS_MASK 				0x1FDFD
+#define SWRM_INTERRUPT_STATUS_MASK                              0x1FDFD
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
-#define SWRM_INTERRUPT_MAX					0x11
+#define SWRM_INTERRUPT_MAX                                      0x11
 #endif /* CONFIG_SWRM_VER_1P7 */
 #endif /* CONFIG_SWRM_VER_2P0 */
 #define SWRM_CMD_FIFO_CMD                         (SWRM_BASE+0x0308)
@@ -120,19 +121,14 @@
 #define SWRM_DOUT_DP_SILENCE_TONE_CFG(n)    (SWRM_BASE+0x1050+0x100*n)
 #define SWRM_DOUT_DP_PCM_PORT_CTRL(n)       (SWRM_BASE+0x1054+0x100*n)
 
-#ifdef CONFIG_SWRM_VER_2P0
-#define SWRM_DOUT_DP_FIFO_WATERMARK_CTRL(n) (SWRM_BASE+0x1060+0x100*n)
-#define SWRM_DIN_DP_INT_STATUS(n)         (SWRM_BASE+0x1900+0x100*n)
-#define SWRM_DIN_DP_INT_CLEAR(n)          (SWRM_BASE+0x1908+0x100*n)
-#define SWRM_DIN_DP_FEATURES_EN(n)        (SWRM_BASE+0x194C+0x100*n)
-#define SWRM_DIN_DP_PCM_PORT_CTRL(n)      (SWRM_BASE+0x1954+0x100*n)
-#define SWRM_MAX_REGISTER SWRM_TO_CPU_SW_MESSAGE_READ(2, 2)
-
-#else
 #define SWRM_DIN_DP_INT_STATUS(n)         (SWRM_BASE+0x1000+0x100*n)
 #define SWRM_DIN_DP_INT_CLEAR(n)          (SWRM_BASE+0x1008+0x100*n)
 #define SWRM_DIN_DP_FEATURES_EN(n)        (SWRM_BASE+0x104C+0x100*n)
 #define SWRM_DIN_DP_PCM_PORT_CTRL(n)      (SWRM_BASE+0x1054+0x100*n)
+
+#ifdef CONFIG_SWRM_VER_2P0
+#define SWRM_MAX_REGISTER SWRM_TO_CPU_SW_MESSAGE_READ(2, 2)
+#else
 #define SWRM_MAX_REGISTER SWRM_DIN_DP_PCM_PORT_CTRL(9)
 #endif /* CONFIG_SWRM_VER_2P0 */
 
@@ -171,13 +167,12 @@
 #define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU3         0x800000
 
 
-#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH		0x00007C00
-#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH		0x000F8000
-
-#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL	0x06
-#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7	0x406
-#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V2P0	0x40E
-#define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK	0x18
+#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                       0x00007C00
+#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                       0x000F8000
 
-#define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES	0x00F00000
+#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL                    0x06
+#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7               0x406
+#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V2P0               0x40E
+#define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK                    0x18
+#define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES                    0x00F00000
 #endif /* _SWRM_REGISTERS_H */