soc: Fix SWRM DIN Addresses and CPS offset1
SWRM_DIN_DP_* registers are based on incorrect register values. Update to match correct hardware addresses. Also fix tabs/spaces mismatch in same file. Fix CPS offset1 port parameter to be 0 instead of 0xff. Change-Id: I641a925f1f3b454a6af0d2491d86459131bba2cf Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
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Matthew Rice
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کامیت
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@@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _KALAMA_PORT_CONFIG
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@@ -29,7 +29,7 @@ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{15, 6, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
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{15, 13, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
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{799, 0xFF, 0xFF, 15, 15, 24, 0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
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{799, 0, 0xFF, 15, 15, 24, 0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
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};
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static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
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@@ -35,11 +35,12 @@
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#define SWRM_LINK_STATUS(n) (SWRM_BASE+0x4064+0x1000*n)
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#define SWRM_TO_CPU_SW_MESSAGE(n, m) (SWRM_BASE+0x4090+0x1000*n+0x4*m)
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#define SWRM_TO_CPU_SW_MESSAGE_READ(n, m) (SWRM_BASE+0x40A0+0x1000*n+0x4*m)
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#define SWRM_DOUT_DP_FIFO_WATERMARK_CTRL(n) (SWRM_BASE+0x1060+0x100*n)
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20
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#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400
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#define SWRM_INTERRUPT_STATUS_MASK 0x1DFDFD
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#define SWRM_INTERRUPT_MAX 0x17
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#define SWRM_INTERRUPT_STATUS_MASK 0x1DFDFD
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#define SWRM_INTERRUPT_MAX 0x17
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#else
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#define SWRM_INTERRUPT_STATUS (SWRM_BASE+0x0200)
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@@ -62,11 +63,11 @@
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#define SWRM_CMD_FIFO_RD_CMD SWRM_CPU1_CMD_FIFO_RD_CMD
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#define SWRM_CMD_FIFO_STATUS SWRM_CPU1_CMD_FIFO_STATUS
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#define SWRM_CMD_FIFO_RD_FIFO SWRM_CPU1_CMD_FIFO_RD_FIFO
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#define SWRM_INTERRUPT_STATUS_MASK 0x1DFDFD
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#define SWRM_INTERRUPT_STATUS_MASK 0x1DFDFD
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x40000
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x80000
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#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x100000
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#define SWRM_INTERRUPT_MAX 0x20
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#define SWRM_INTERRUPT_MAX 0x20
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#else
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#define SWRM_INTERRUPT_EN (SWRM_BASE+0x0204)
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#define SWRM_INTERRUPT_EN_1 (SWRM_BASE+0x0224)
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@@ -74,11 +75,11 @@
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#define SWRM_CMD_FIFO_RD_CMD (SWRM_BASE+0x0304)
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#define SWRM_CMD_FIFO_STATUS (SWRM_BASE+0x030C)
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#define SWRM_CMD_FIFO_RD_FIFO (SWRM_BASE+0x0318)
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#define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
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#define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10
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#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20
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#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400
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#define SWRM_INTERRUPT_MAX 0x11
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#define SWRM_INTERRUPT_MAX 0x11
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#endif /* CONFIG_SWRM_VER_1P7 */
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#endif /* CONFIG_SWRM_VER_2P0 */
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#define SWRM_CMD_FIFO_CMD (SWRM_BASE+0x0308)
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@@ -120,19 +121,14 @@
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#define SWRM_DOUT_DP_SILENCE_TONE_CFG(n) (SWRM_BASE+0x1050+0x100*n)
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#define SWRM_DOUT_DP_PCM_PORT_CTRL(n) (SWRM_BASE+0x1054+0x100*n)
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#ifdef CONFIG_SWRM_VER_2P0
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#define SWRM_DOUT_DP_FIFO_WATERMARK_CTRL(n) (SWRM_BASE+0x1060+0x100*n)
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#define SWRM_DIN_DP_INT_STATUS(n) (SWRM_BASE+0x1900+0x100*n)
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#define SWRM_DIN_DP_INT_CLEAR(n) (SWRM_BASE+0x1908+0x100*n)
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#define SWRM_DIN_DP_FEATURES_EN(n) (SWRM_BASE+0x194C+0x100*n)
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#define SWRM_DIN_DP_PCM_PORT_CTRL(n) (SWRM_BASE+0x1954+0x100*n)
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#define SWRM_MAX_REGISTER SWRM_TO_CPU_SW_MESSAGE_READ(2, 2)
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#else
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#define SWRM_DIN_DP_INT_STATUS(n) (SWRM_BASE+0x1000+0x100*n)
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#define SWRM_DIN_DP_INT_CLEAR(n) (SWRM_BASE+0x1008+0x100*n)
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#define SWRM_DIN_DP_FEATURES_EN(n) (SWRM_BASE+0x104C+0x100*n)
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#define SWRM_DIN_DP_PCM_PORT_CTRL(n) (SWRM_BASE+0x1054+0x100*n)
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#ifdef CONFIG_SWRM_VER_2P0
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#define SWRM_MAX_REGISTER SWRM_TO_CPU_SW_MESSAGE_READ(2, 2)
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#else
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#define SWRM_MAX_REGISTER SWRM_DIN_DP_PCM_PORT_CTRL(9)
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#endif /* CONFIG_SWRM_VER_2P0 */
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@@ -171,13 +167,12 @@
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#define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU3 0x800000
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#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH 0x00007C00
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#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH 0x000F8000
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#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH 0x00007C00
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#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH 0x000F8000
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL 0x06
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7 0x406
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V2P0 0x40E
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#define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK 0x18
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#define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES 0x00F00000
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL 0x06
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7 0x406
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#define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V2P0 0x40E
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#define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK 0x18
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#define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES 0x00F00000
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#endif /* _SWRM_REGISTERS_H */
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