soc: swr-mstr-ctrl: Update SWR V1.6 registers

Update swr ver 1.6 registers.

Change-Id: I074a22305915b2ca38b6d6107fa253a435f92214
Signed-off-by: Soumya Managoli <[email protected]>

soc/swr-mstr-ctrl.c

@@ -705,7 +705,11 @@ static bool swrm_check_link_status(struct swr_mstr_ctrl *swrm, bool active)
 		return true;
 
 	do {
+#ifdef CONFIG_SWRM_VER_2P0
 		comp_sts = swr_master_read(swrm, SWRM_LINK_STATUS(swrm->ee_val)) & 0x01;
+#else
+		comp_sts = swr_master_read(swrm, SWRM_COMP_STATUS) & 0x01;
+#endif
 		/* check comp status and status requested met */
 		if ((comp_sts && status) || (!comp_sts && !status)) {
 			ret = true;
@@ -2293,9 +2297,9 @@ handle_irq:
 			break;
 		}
 	}
+
 	swr_master_write(swrm, SWRM_INTERRUPT_CLEAR(swrm->ee_val), intr_sts);
 	swr_master_write(swrm, SWRM_INTERRUPT_CLEAR(swrm->ee_val), 0x0);
-
 	if (swrm->enable_slave_irq) {
 		/* Enable slave irq here */
 		swrm_enable_slave_irq(swrm);
@@ -2611,8 +2615,10 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm)
 		reg[len] = SWRM_LINK_MANAGER_EE;
 		value[len++] = swrm->ee_val;
 	}
+#ifdef CONFIG_SWRM_VER_2P0
 	reg[len] = SWRM_CLK_CTRL(swrm->ee_val);
 	value[len++] = 0x01;
+#endif
 
 	/* Set IRQ to PULSE */
 	reg[len] = SWRM_COMP_CFG;
@@ -3302,8 +3308,12 @@ static int swrm_runtime_resume(struct device *dev)
 				iowrite32(temp, swrm->swrm_hctl_reg);
 			}
 			/*wake up from clock stop*/
+#ifdef CONFIG_SWRM_VER_2P0
 			swr_master_write(swrm,
 				SWRM_CLK_CTRL(swrm->ee_val), 0x01);
+#else
+			swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x2);
+#endif
 			/* clear and enable bus clash interrupt */
 			swr_master_write(swrm,
 				SWRM_INTERRUPT_CLEAR(swrm->ee_val), 0x08);

soc/swr-mstr-registers.h

@@ -43,18 +43,18 @@
 #define SWRM_INTERRUPT_MAX                                      0x17
 
 #else
-#define SWRM_INTERRUPT_STATUS                     (SWRM_BASE+0x0200)
-#define SWRM_INTERRUPT_CLEAR                      (SWRM_BASE+0x0208)
-#define SWRM_INTERRUPT_STATUS_1                   (SWRM_BASE+0x0220)
-#define SWRM_INTERRUPT_CLEAR_1                    (SWRM_BASE+0x0228)
-#define SWRM_CPU1_INTERRUPT_EN                    (SWRM_BASE+0x0210)
-#define SWRM_CPU1_INTERRUPT_EN_1                  (SWRM_BASE+0x0230)
-#define SWRM_CPU0_CMD_RESPONSE                    (SWRM_BASE+0x0250)
-
-#define SWRM_CPU1_CMD_FIFO_WR_CMD                 (SWRM_BASE+0x031C)
-#define SWRM_CPU1_CMD_FIFO_RD_CMD                 (SWRM_BASE+0x0320)
-#define SWRM_CPU1_CMD_FIFO_STATUS                 (SWRM_BASE+0x0328)
-#define SWRM_CPU1_CMD_FIFO_RD_FIFO                (SWRM_BASE+0x0334)
+#define SWRM_INTERRUPT_STATUS(n)                  (SWRM_BASE+0x0200*n)
+#define SWRM_INTERRUPT_CLEAR(n)                   (SWRM_BASE+0x0208*n)
+#define SWRM_INTERRUPT_STATUS_1(n)                (SWRM_BASE+0x0220*n)
+#define SWRM_INTERRUPT_CLEAR_1(n)                 (SWRM_BASE+0x0228*n)
+#define SWRM_CPU1_INTERRUPT_EN(n)                 (SWRM_BASE+0x0210*n)
+#define SWRM_CPU1_INTERRUPT_EN_1(n)               (SWRM_BASE+0x0230*n)
+#define SWRM_CPU0_CMD_RESPONSE(n)                 (SWRM_BASE+0x0250*n)
+
+#define SWRM_CPU1_CMD_FIFO_WR_CMD(n)              (SWRM_BASE+0x031C*n)
+#define SWRM_CPU1_CMD_FIFO_RD_CMD(n)              (SWRM_BASE+0x0320*n)
+#define SWRM_CPU1_CMD_FIFO_STATUS(n)              (SWRM_BASE+0x0328*n)
+#define SWRM_CPU1_CMD_FIFO_RD_FIFO(n)             (SWRM_BASE+0x0334*n)
 
 #ifdef CONFIG_SWRM_VER_1P7
 #define SWRM_INTERRUPT_EN                    SWRM_CPU1_INTERRUPT_EN
@@ -69,12 +69,12 @@
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x100000
 #define SWRM_INTERRUPT_MAX                                      0x20
 #else
-#define SWRM_INTERRUPT_EN                         (SWRM_BASE+0x0204)
-#define SWRM_INTERRUPT_EN_1                       (SWRM_BASE+0x0224)
-#define SWRM_CMD_FIFO_WR_CMD                      (SWRM_BASE+0x0300)
-#define SWRM_CMD_FIFO_RD_CMD                      (SWRM_BASE+0x0304)
-#define SWRM_CMD_FIFO_STATUS                      (SWRM_BASE+0x030C)
-#define SWRM_CMD_FIFO_RD_FIFO                     (SWRM_BASE+0x0318)
+#define SWRM_INTERRUPT_EN(n)                      SWRM_CPU1_INTERRUPT_EN(n)
+#define SWRM_INTERRUPT_EN_1(n)                    (SWRM_BASE+0x0224*n)
+#define SWRM_CMD_FIFO_WR_CMD(n)                   (SWRM_BASE+0x0300*n)
+#define SWRM_CMD_FIFO_RD_CMD(n)                   (SWRM_BASE+0x0304*n)
+#define SWRM_CMD_FIFO_STATUS(n)                   (SWRM_BASE+0x030C*n)
+#define SWRM_CMD_FIFO_RD_FIFO(n)                  (SWRM_BASE+0x0318*n)
 #define SWRM_INTERRUPT_STATUS_MASK                              0x1FDFD
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20