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android_kernel_...
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soc
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swr-mstr-registers.h

swr-mstr-registers.h 10 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2015, 2018-2021 The Linux Foundation. All rights reserved.
    4. 

  4.  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _SWRM_REGISTERS_H
    8. 

  8. #define _SWRM_REGISTERS_H
    9. 

  9. 

  10. #define SWRM_BASE                                 0x00
    11. 

  11. #define SWRM_COMP_HW_VERSION                      (SWRM_BASE+0x0000)
    12. 

  12. #define SWRM_COMP_CFG                             (SWRM_BASE+0x0004)
    13. 

  13. #define SWRM_COMP_SW_RESET                        (SWRM_BASE+0x0008)
    14. 

  14. #define SWRM_COMP_POWER_CFG                       (SWRM_BASE+0x000C)
    15. 

  15. #define SWRM_COMP_FEATURE_CFG                     (SWRM_BASE+0x0010)
    16. 

  16. #define SWRM_COMP_STATUS                          (SWRM_BASE+0x0014)
    17. 

  17. #define SWRM_LINK_MANAGER_EE                      (SWRM_BASE+0x0018)
    18. 

  18. #define SWRM_COMP_PARAMS                          (SWRM_BASE+0x0100)
    19. 

  19. #define SWRM_COMP_MASTER_ID                       (SWRM_BASE+0x0104)
    20. 

  20. #define MM_SYNC_CONFIG                            (SWRM_BASE+0x0108)
    21. 

  21. #define SWRM_COMP_NPL_PARAMS                      (SWRM_BASE+0x0120)
    22. 

  22. 

  23. #ifdef CONFIG_SWRM_VER_2P0
    24. 

  24. #define SWRM_INTERRUPT_STATUS(n)          (SWRM_BASE+0x4000+0x1000*n)
    25. 

  25. #define SWRM_INTERRUPT_EN(n)              (SWRM_BASE+0x4004+0x1000*n)
    26. 

  26. #define SWRM_INTERRUPT_CLEAR(n)           (SWRM_BASE+0x4008+0x1000*n)
    27. 

  27. #define SWRM_CMD_FIFO_WR_CMD(n)           (SWRM_BASE+0x4020+0x1000*n)
    28. 

  28. #define SWRM_CMD_FIFO_RD_CMD(n)           (SWRM_BASE+0x4024+0x1000*n)
    29. 

  29. #define SWRM_NUM_ENTRIES_CMD_FIFO(n)      (SWRM_BASE+0x4028+0x1000*n)
    30. 

  30. #define SWRM_CMD_FIFO_RD_FIFO(n)          (SWRM_BASE+0x4040+0x1000*n)
    31. 

  31. #define SWRM_NUM_ENTRIES_RD_FIFO(n)       (SWRM_BASE+0x4044+0x1000*n)
    32. 

  32. #define SWRM_CMD_FIFO_STATUS(n)           (SWRM_BASE+0x4050+0x1000*n)
    33. 

  33. #define SWRM_CMD_RESPONSE(n)              (SWRM_BASE+0x4054+0x1000*n)
    34. 

  34. #define SWRM_CLK_CTRL(n)                  (SWRM_BASE+0x4060+0x1000*n)
    35. 

  35. #define SWRM_LINK_STATUS(n)               (SWRM_BASE+0x4064+0x1000*n)
    36. 

  36. #define SWRM_TO_CPU_SW_MESSAGE(n, m)      (SWRM_BASE+0x4090+0x1000*n+0x4*m)
    37. 

  37. #define SWRM_TO_CPU_SW_MESSAGE_READ(n, m) (SWRM_BASE+0x40A0+0x1000*n+0x4*m)
    38. 

  38. #define SWRM_DOUT_DP_FIFO_WATERMARK_CTRL(n) (SWRM_BASE+0x1060+0x100*n)
    39. 

  39. #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
    40. 

  40. #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
    41. 

  41. #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
    42. 

  42. #define SWRM_INTERRUPT_STATUS_MASK                              0x1DFDFD
    43. 

  43. #define SWRM_INTERRUPT_MAX                                      0x17
    44. 

  44. 

  45. #else
    46. 

  46. #define SWRM_INTERRUPT_STATUS(n)                  (SWRM_BASE+0x0200*n)
    47. 

  47. #define SWRM_INTERRUPT_CLEAR(n)                   (SWRM_BASE+0x0208*n)
    48. 

  48. #define SWRM_INTERRUPT_STATUS_1(n)                (SWRM_BASE+0x0220*n)
    49. 

  49. #define SWRM_INTERRUPT_CLEAR_1(n)                 (SWRM_BASE+0x0228*n)
    50. 

  50. #define SWRM_CPU1_INTERRUPT_EN(n)                 (SWRM_BASE+0x0210*n)
    51. 

  51. #define SWRM_CPU1_INTERRUPT_EN_1(n)               (SWRM_BASE+0x0230*n)
    52. 

  52. #define SWRM_CPU0_CMD_RESPONSE(n)                 (SWRM_BASE+0x0250*n)
    53. 

  53. 

  54. #define SWRM_CPU1_CMD_FIFO_WR_CMD(n)              (SWRM_BASE+0x031C*n)
    55. 

  55. #define SWRM_CPU1_CMD_FIFO_RD_CMD(n)              (SWRM_BASE+0x0320*n)
    56. 

  56. #define SWRM_CPU1_CMD_FIFO_STATUS(n)              (SWRM_BASE+0x0328*n)
    57. 

  57. #define SWRM_CPU1_CMD_FIFO_RD_FIFO(n)             (SWRM_BASE+0x0334*n)
    58. 

  58. 

  59. #ifdef CONFIG_SWRM_VER_1P7
    60. 

  60. #define SWRM_INTERRUPT_EN                    SWRM_CPU1_INTERRUPT_EN
    61. 

  61. #define SWRM_INTERRUPT_EN_1                  SWRM_CPU1_INTERRUPT_EN_1
    62. 

  62. #define SWRM_CMD_FIFO_WR_CMD                 SWRM_CPU1_CMD_FIFO_WR_CMD
    63. 

  63. #define SWRM_CMD_FIFO_RD_CMD                 SWRM_CPU1_CMD_FIFO_RD_CMD
    64. 

  64. #define SWRM_CMD_FIFO_STATUS                 SWRM_CPU1_CMD_FIFO_STATUS
    65. 

  65. #define SWRM_CMD_FIFO_RD_FIFO                SWRM_CPU1_CMD_FIFO_RD_FIFO
    66. 

  66. #define SWRM_INTERRUPT_STATUS_MASK                              0x1DFDFD
    67. 

  67. #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x40000
    68. 

  68. #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x80000
    69. 

  69. #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x100000
    70. 

  70. #define SWRM_INTERRUPT_MAX                                      0x20
    71. 

  71. #else
    72. 

  72. #define SWRM_INTERRUPT_EN(n)                      SWRM_CPU1_INTERRUPT_EN(n)
    73. 

  73. #define SWRM_INTERRUPT_EN_1(n)                    (SWRM_BASE+0x0224*n)
    74. 

  74. #define SWRM_CMD_FIFO_WR_CMD(n)                   (SWRM_BASE+0x0300*n)
    75. 

  75. #define SWRM_CMD_FIFO_RD_CMD(n)                   (SWRM_BASE+0x0304*n)
    76. 

  76. #define SWRM_CMD_FIFO_STATUS(n)                   (SWRM_BASE+0x030C*n)
    77. 

  77. #define SWRM_CMD_FIFO_RD_FIFO(n)                  (SWRM_BASE+0x0318*n)
    78. 

  78. #define SWRM_INTERRUPT_STATUS_MASK                              0x1FDFD
    79. 

  79. #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  0x10
    80. 

  80. #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 0x20
    81. 

  81. #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           0x400
    82. 

  82. #define SWRM_INTERRUPT_MAX                                      0x11
    83. 

  83. #endif /* CONFIG_SWRM_VER_1P7 */
    84. 

  84. #endif /* CONFIG_SWRM_VER_2P0 */
    85. 

  85. #define SWRM_CMD_FIFO_CMD                         (SWRM_BASE+0x0308)
    86. 

  86. #define SWRM_CMD_FIFO_CFG                         (SWRM_BASE+0x0314)
    87. 

  87. #define SWRM_CPU_NUM_ENTRIES_WR_CMD_FIFO          (SWRM_BASE+0x0370)
    88. 

  88. #define SWRM_CPU0_SW_INTERRUPT_SET                (SWRM_BASE+0x0374)
    89. 

  89. #define SWRM_CPU0_SW_MESSAGE0                     (SWRM_BASE+0x0384)
    90. 

  90. #define SWRM_CPU0_SW_MESSAGE1                     (SWRM_BASE+0x0394)
    91. 

  91. #define SWRM_ENUMERATOR_CFG                       (SWRM_BASE+0x0500)
    92. 

  92. #define SWRM_ENUMERATOR_STATUS                    (SWRM_BASE+0x0504)
    93. 

  93. #define SWRM_ENUMERATOR_PRE_ENUM_CFG              (SWRM_BASE+0x0530)
    94. 

  94. #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)         (SWRM_BASE+0x0530+0x8*m)
    95. 

  95. #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)         (SWRM_BASE+0x0534+0x8*m)
    96. 

  96. #define SWRM_CTRL_W_GEN_STATUS                    (SWRM_BASE+0x0600)
    97. 

  97. #define SWRM_SW_RESET_STATUS                      (SWRM_BASE+0x0700)
    98. 

  98. #define SWRM_FORCE_BANK_SWITCH_SUCCESS            (SWRM_BASE+0x0704)
    99. 

  99. #define SWRM_SILENCE_TONE_REPEAT_VALUE_THRESHOLD  (SWRM_BASE+0x0710)
    100. 

  100. #define SWRM_SELF_GENERATE_FRAME_SYNC             (SWRM_BASE+0x0714)
    101. 

  101. #define SWRM_MCP_FRAME_CTRL_BANK(m)               (SWRM_BASE+0x101C+0x40*m)
    102. 

  102. #define SWRM_MCP_BUS_CTRL                         (SWRM_BASE+0x1044)
    103. 

  103. #define SWRM_MCP_CFG                              (SWRM_BASE+0x1048)
    104. 

  104. #define SWRM_MCP_STATUS                           (SWRM_BASE+0x104C)
    105. 

  105. #define SWRM_MCP_SLV_STATUS                       (SWRM_BASE+0x1090)
    106. 

  106. 

  107. 

  108. #define SWRM_DP_PORT_CONTROL(n)           (SWRM_BASE+0x1020+0x100*n)
    109. 

  109. #define SWRM_DP_PORT_CTRL_BANK(n, m)      (SWRM_BASE+0x1024+0x100*n+0x40*m)
    110. 

  110. #define SWRM_DP_PORT_CTRL_2_BANK(n, m)    (SWRM_BASE+0x1028+0x100*n+0x40*m)
    111. 

  111. #define SWRM_DP_BLOCK_CTRL_1(n)           (SWRM_BASE+0x102C+0x100*n)
    112. 

  112. #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)    (SWRM_BASE+0x1030+0x100*n+0x40*m)
    113. 

  113. #define SWRM_DP_PORT_HCTRL_BANK(n, m)     (SWRM_BASE+0x1034+0x100*n+0x40*m)
    114. 

  114. #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)    (SWRM_BASE+0x1038+0x100*n+0x40*m)
    115. 

  115. #define SWRM_DP_SAMPLECTRL2_BANK(n, m)    (SWRM_BASE+0x103C+0x100*n+0x40*m)
    116. 

  116. 

  117. 

  118. #define SWRM_DOUT_DP_INT_STATUS(n)          (SWRM_BASE+0x1000+0x100*n)
    119. 

  119. #define SWRM_DOUT_DP_INT_CLEAR(n)           (SWRM_BASE+0x1008+0x100*n)
    120. 

  120. #define SWRM_DOUT_DP_FEATURES_EN(n)         (SWRM_BASE+0x104C+0x100*n)
    121. 

  121. #define SWRM_DOUT_DP_SILENCE_TONE_CFG(n)    (SWRM_BASE+0x1050+0x100*n)
    122. 

  122. #define SWRM_DOUT_DP_PCM_PORT_CTRL(n)       (SWRM_BASE+0x1054+0x100*n)
    123. 

  123. 

  124. #define SWRM_DIN_DP_INT_STATUS(n)         (SWRM_BASE+0x1000+0x100*n)
    125. 

  125. #define SWRM_DIN_DP_INT_CLEAR(n)          (SWRM_BASE+0x1008+0x100*n)
    126. 

  126. #define SWRM_DIN_DP_FEATURES_EN(n)        (SWRM_BASE+0x104C+0x100*n)
    127. 

  127. #define SWRM_DIN_DP_PCM_PORT_CTRL(n)      (SWRM_BASE+0x1054+0x100*n)
    128. 

  128. 

  129. #ifdef CONFIG_SWRM_VER_2P0
    130. 

  130. #define SWRM_MAX_REGISTER SWRM_TO_CPU_SW_MESSAGE_READ(2, 2)
    131. 

  131. #else
    132. 

  132. #define SWRM_MAX_REGISTER SWRM_DIN_DP_PCM_PORT_CTRL(9)
    133. 

  133. #endif /* CONFIG_SWRM_VER_2P0 */
    134. 

  134. 

  135. 

  136. #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    0x1
    137. 

  137. #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                0x2
    138. 

  138. #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          0x4
    139. 

  139. #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  0x8
    140. 

  140. #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              0x40
    141. 

  141. #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         0x80
    142. 

  142. #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               0x100
    143. 

  143. #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         0x200
    144. 

  144. 

  145. #ifdef CONFIG_SWRM_VER_1P1
    146. 

  146. #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED   0x800
    147. 

  147. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED               0x1000
    148. 

  148. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL        0x2000
    149. 

  149. #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED             0x4000
    150. 

  150. #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED              0x8000
    151. 

  151. #define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST                0x10000
    152. 

  152. #else
    153. 

  153. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED               0x800
    154. 

  154. #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL        0x1000
    155. 

  155. #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED             0x2000
    156. 

  156. #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED              0x4000
    157. 

  157. #define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST                0x8000
    158. 

  158. #endif /* CONFIG_SWRM_VER_1P1 */
    159. 

  159. 

  160. #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP            0x10000
    161. 

  161. #define SWRM_INTERRUPT_STATUS_DOUT_RATE_MISMATCH             0x20000
    162. 

  162. #define SWRM_INTERRUPT_STATUS_BUS_REL_REQUEST_NON_MONITOR_MODE 0x40000
    163. 

  163. #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED 0x80000
    164. 

  164. #define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU0         0x100000
    165. 

  165. #define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU1         0x200000
    166. 

  166. #define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU2         0x400000
    167. 

  167. #define SWRM_INTERRUPT_STATUS_SW_INTERRUPT_FROM_CPU3         0x800000
    168. 

  168. 

  169. 

  170. #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                       0x00007C00
    171. 

  171. #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                       0x000F8000
    172. 

  172. 

  173. #define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL                    0x06
    174. 

  174. #define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7               0x406
    175. 

  175. #define SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V2P0               0x40E
    176. 

  176. #define SWRM_COMP_FEATURE_CFG_PCM_EN_MASK                    0x18
    177. 

  177. #define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES                    0x00F00000
    178. 

  178. #endif /* _SWRM_REGISTERS_H */
    179.