This change fixes the issue in selecting the correct
perf index for the 90Hz refresh rate, before this change
values corresponding to 60Hz were getting applied for this
refresh rate.
Change-Id: Id4f8af4da95f0d13d30f6316dc26dd65b61d7f79
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
For existing HW, in-line rotation is only supported on master
planes. Remove publishing support for rotate-90 and rotate-270
on all virtual planes. Also, fixup the published support for
180 degree rotation which can be performed on all pipes that
have both X & Y axes reflections.
Change-Id: Iff248abeefeb2a100ffd833d94b429b47b6d407b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Update the uidle wd timer load value to 18. This change will allow
a 15us wd timer per hardware recommendation.
Update fal1 threshold value to take the minimum of 15 or the
current setting which takes line time and target idle time into
consideration. The target idle time is also being updated from 10us to
40us.
Change-Id: Ia8d9c2070813beef18fdf342526d82cf8f82989b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Current SDE driver allows staging of rect1 only configuration. When a
real plane is disabled sspp multi rect configuration is not updated.
This can lead to iommu faults and ping pong timeouts as framebuffer of
disabled plane is unmapped. This change fixes it by updating multi rect
config accordingly when a plane is disabled.
Change-Id: I67ae45ad0e607184c7fc49f4b220220ba1d8a2ae
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Allow caller to specify the default value of the enum
property while installing with msm prop layer. It is
not always the case that the default value to be the
first entry.
Change-Id: Ie0bb1ad7479e3e07810b3d817fdf618b1935858c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
QSEED scalar block HW revision is constant for a given MDSS revision.
Both SSPP and DS HW files invoke this API to read the revision register
at various points of time. Expose this revision information through
DT binding and maintain in the catalog to avoid repeated register
reads.
Change-Id: I95c0a5242cfda0aaa4ec5c2ff5c7cc0bed191b59
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
SDE driver started supporting multirect mode with rect_1 only
configuration. In such case, master plane can not trigger
pipe fetch halt independently. This change removes the pipe
fetch halt check completely because it was only done for
master plane without buffer flip usecase. AXI fetch halt
provides similar functionality during idle power collapse
and suspend-resume.
Change-Id: I79d9d0eac2de95f1bb88561c7cc259e0cc4b2ca4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
In targets where ubwc is not supported, atomic check
should fail and return a error value if the input format
is ubwc.
Change-Id: I21a40f510cc852e64fbcc05a5fb4848da4b4faaa
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
This change addresses out of range and null checks in
sde driver.
Change-Id: I4ee82760ce3ee7053c336e49ec9eaae8b4c31b1e
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
In current driver if client did not reset system cache
crtc property, system cache write state is on forever and
breaks the system cache feature. This change restricts
entering into cache write state only if it's commit right
after idle notify. This change also adds event logs to
capture system cache feature state changes.
Change-Id: Ie46fc9113f752ed8989dab99301690a13003b00b
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Add smmu cache hint at during the msm gem prime import
to ensure memory is cacheable. Ensure sys cache feature
is added to all sspp, not just vig.
Change-Id: Icc10468ad8d3e7c6aabd437776cde99eb627375a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Add plane buffer flag to get the correct aspace during
TUI VM usecase. FB_NON_SEC_DIR_TRANS plane flag is set
by user-mode to indicate S2-only non-secure buffer in
TUI VM. Return the default drm device when SMMU is not
available during get_aspace_device to make the working
seamless with/without SMMU.
Change-Id: I158dc17ba51ff4b2f302d3e7017db8ab3cfe2b84
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add SID setup function to help programming
the SIDs for all the pipes and lutdma xin clients
based on the VM.
Change-Id: Iea598303b480b33de8750e0988129dd5cdfe7572
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.
This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.
Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Currently, the value for predownscale_x_0 is being set based
on source height and destination height. This value should only
be set if userspace has not set a value for it already or if
default scale is enabled through debugfs.
Change-Id: Icf13ac33ae4a1a40bff90cd639428e9a11f96241
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Lower the cyclomatic complexity for this function by splitting the
work into helper functions.
Change-Id: I07d399e455ca2f73a14875b45c30f123c39fa501
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add scaling linewidth variable and logic changes to get
valid max linewidth values for inline rotation and scaling.
Modify linewidth check to compare with scaler source width.
Change-Id: I7c63175e568ecb524f9cdf8ada1d7c6fdc999236
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
Updating qos remap updates requires reading registers to update values,
this adds additional CPU processing when in reality this update
is only needed once.
Bug: 142504774
Change-Id: Iec8d4dfd858b0602db7d2275b6b716dbcffe0d2f
(cherry picked from commit dbd1cfbc21db4b9bd4f1a4fc234cedc314fa1265)
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change introduces pre-downscaling values to the path where
these values are not provided by userspace. Currently, pre-downscaling
is only allowed by a factor of 2.2 in the x direction. With this
change pre-downscaling will support >2.2 up to 4 in the x direction.
Change-Id: I04d1b07243a5973e9338ea2a212280985b31b6a3
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Lower the cyclomatic code complexity by moving some logic into
a helper function.
Change-Id: If15a4eaaecb0f6eec512671d47e4da20f9a31670
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.
Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Some of the features in the DPU hardware needs planes to be staged but
it should not be blended in the layer mixer. Change adds support for drm
driver client to set the blend type on the plane and updates driver code
to skip staging the plane.
Change-Id: I1e8c7f6ce5617820ea8b24419e0d4d27b481819b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Demura block of dpu will use the register dma path for programming.
Change updates the register dma frame-work to allow programming of the
demura block.
Change-Id: Ie5a64df1b2fffcb84d9554e5211249892ed2d96d
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Based on the hardware catalog if dpu supports demura, driver will
install the drm properties specific to the feature. Change added support
for creating demura properties and exposing via drm frame-work.
Change-Id: I58f5b12ca660d826e6e0b7e1f212bdf3c5e41905
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
This change addresses out of range and null checks in
sde driver.
Change-Id: I905d795edf6715aa990dd7bbaf061734e95ddea6
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add framebuffer destroy immediately following plane cleanup
during secure display transition. Set state's fb to NULL
after destroying to avoid attempting to destroy fb again
during plane state destroy. Previously, framebuffer destroy
is happening after the context is detached while plane states
are being destroyed.
Change-Id: I273ce5b85c30962ea7e0a738a366487c9c85d4df
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.
Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
In dual display continuous splash case, there are certain
scenarios where pipe being used in secondary display at boot up
is allocated by primary crtc. Add check to return failure
in such cases.
Change-Id: I9047b6e7f91e59a9daff5089abb41017c068b449
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Separate the horizontal and vertical max downscale checks
as pre-downscale introduced different limits on different
axes. Also cleanup the variable names for max downscale
limit when pre-downscale is not enabled.
Change-Id: If01aac1844d0bd5133502a50dbc38197e11da5d5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The original change avoids unnecessary reprogramming
of plane vbif registers, but still copies values into
a local struct before exiting based on boolean. This
can be taken care of by 01e1d4136cc1 ("drm/msm:
minimize qos remap updates") instead.
This reverts commit 0c7159de4f.
Change-Id: Idd9b066db9ebad092aa1a6dd2cf47050b0babd0c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Support different safe, danger and creq qos lut
configuration based on display fps. It also removes
the fill level calculations from sspp and wb block
because mdss hw supports simple configuration.
Change-Id: I203e4300c9eab27d3632c890bedd6383cca0e5a8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Legacy HW that does not support pre-downscale capability will
incorrectly fail certain scaling checks. Fix those checks to
fully support HW without pre-downscaler.
Change-Id: I8f645bbff959e176c1d4d05a30a580113e320d4b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The pre-downscale capability is checked in multiple places
within sde_plane.c file. Add a helper function to check this
capability flag instead of manually checking this bit.
Change-Id: I21f818a9d81dd63e5eb3da248532904cfa55c838
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
During plane setup, when a master plane ID is provided it means we
are initializing a slave plane for HW shared by the given master ID.
When master plane ID is 0 it means this is the master. This change
refactors the code to make this clear.
Change-Id: Ia2e3430e6f9f7e105eaf26f121753b676110abe5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
De-couple the horizontal and vertical pre-downscale checks since
this block can be used in cases where only X-axis downscaling
is needed.
Change-Id: I2e7d30863baed98e9f7fa0a328837691f0bc75a5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
