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@@ -80,6 +80,8 @@
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REG_DMA_HEADERS_BUFFER_SZ)
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#define SPR_INIT_MEM_SIZE ((sizeof(struct drm_msm_spr_init_cfg)) + \
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REG_DMA_HEADERS_BUFFER_SZ)
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+#define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \
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+ REG_DMA_HEADERS_BUFFER_SZ)
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#define REG_MASK(n) ((BIT(n)) - 1)
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#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
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@@ -142,6 +144,7 @@ static u32 feature_map[SDE_DSPP_MAX] = {
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[SDE_DSPP_HIST] = REG_DMA_FEATURES_MAX,
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[SDE_DSPP_AD] = REG_DMA_FEATURES_MAX,
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[SDE_DSPP_RC] = RC_DATA,
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+ [SDE_DSPP_DEMURA] = DEMURA_CFG,
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};
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static u32 sspp_feature_map[SDE_SSPP_MAX] = {
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@@ -170,6 +173,7 @@ static u32 feature_reg_dma_sz[SDE_DSPP_MAX] = {
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[SDE_DSPP_MEMCOLOR] = MEMCOLOR_MEM_SIZE,
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[SDE_DSPP_RC] = RC_MEM_SIZE,
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[SDE_DSPP_SPR] = SPR_INIT_MEM_SIZE,
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+ [SDE_DSPP_DEMURA] = DEMURA_MEM_SIZE,
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};
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static u32 sspp_feature_reg_dma_sz[SDE_SSPP_MAX] = {
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@@ -4693,3 +4697,552 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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}
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+
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+static void reg_dma_demura_off(struct sde_hw_dspp *ctx,
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+ struct sde_hw_cp_cfg *hw_cfg)
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+{
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+ struct sde_hw_reg_dma_ops *dma_ops;
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+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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+ struct sde_reg_dma_kickoff_cfg kick_off;
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+ u32 demura_base = ctx->cap->sblk->demura.base;
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+ u32 op_mode = 0;
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+ int rc;
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+
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+ dma_ops = sde_reg_dma_get_ops();
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+ dma_ops->reset_reg_dma_buf(dspp_buf[DEMURA_CFG][ctx->idx]);
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+
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+ REG_DMA_INIT_OPS(dma_write_cfg, MDSS, DEMURA_CFG,
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+ dspp_buf[DEMURA_CFG][ctx->idx]);
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+
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+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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+ rc = dma_ops->setup_payload(&dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("write decode select failed ret %d\n", rc);
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+ return;
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+ }
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+
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+ REG_DMA_SETUP_OPS(dma_write_cfg, ctx->hw.blk_off + demura_base + 0x4,
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+ &op_mode, sizeof(op_mode), REG_SINGLE_WRITE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(&dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("off(0x4): REG_SINGLE_WRITE failed ret %d\n", rc);
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+ return;
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+ }
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+
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+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
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+ dspp_buf[DEMURA_CFG][ctx->idx],
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+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
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+
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+ rc = dma_ops->kick_off(&kick_off);
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+ if (rc)
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+ DRM_ERROR("failed to kick off ret %d\n", rc);
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+}
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+
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+static int __reg_dmav1_setup_demurav1_cfg0_c_params(
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+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
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+ struct drm_msm_dem_cfg *dcfg,
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+ struct sde_hw_reg_dma_ops *dma_ops,
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+ u32 *temp, u32 temp_sz, u32 comp_index,
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+ u32 demura_base)
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+{
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+ u32 i, len;
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+ u64 *p;
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+ int rc;
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+
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+ if (temp_sz < ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8 || comp_index > 2) {
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+ DRM_ERROR("exp sz %zd act sz %d comp index %d\n",
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+ ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8,
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+ temp_sz, comp_index);
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+ return -EINVAL;
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+ }
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+
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+ memset(temp, 0x0, ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8);
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+ if (comp_index == 0) {
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+ len = 1 << dcfg->c0_depth;
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+ p = dcfg->cfg0_param2_c0;
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+ } else if (comp_index == 1) {
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+ len = 1 << dcfg->c1_depth;
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+ p = dcfg->cfg0_param2_c1;
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+ } else {
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+ len = 1 << dcfg->c2_depth;
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+ p = dcfg->cfg0_param2_c2;
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+ }
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+
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+ if (!len || len > 256) {
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+ DRM_ERROR("invalid len %d Max 256\n", len);
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+ return -EINVAL;
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+ }
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+
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+ i = ((comp_index & 0x3) << 28) | BIT(31);
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x68,
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+ &i, sizeof(i), REG_SINGLE_WRITE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x68: REG_SINGLE_WRITE failed ret %d\n", rc);
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+ return rc;
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+ }
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+
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+ for (i = 0; i < len; i++) {
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+ temp[i * 2] = p[i] & REG_MASK(32);
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+ temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT(10, 32)) >> 32;
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+ DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
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+ i * 2, temp[i * 2]);
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+ DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
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+ i * 2 + 1, temp[i * 2 + 1]);
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+ }
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x6c,
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+ temp, sizeof(u64) * len, REG_BLK_WRITE_INC, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x6c: REG_BLK_WRITE_INC failed ret %d\n", rc);
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+ return rc;
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+ }
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+ return rc;
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+}
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+
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+static int __reg_dmav1_setup_demurav1_cfg0(struct sde_hw_dspp *ctx,
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+ struct drm_msm_dem_cfg *dcfg,
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+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
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+ struct sde_hw_reg_dma_ops *dma_ops,
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+ struct sde_hw_cp_cfg *hw_cfg)
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+{
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+ u32 *temp = NULL, i, *p = NULL, shift, width;
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+ int rc;
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+ u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
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+
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+ if (!dcfg->cfg0_en) {
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+ DRM_DEBUG_DRIVER("dcfg->cfg0_en is disabled\n");
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+ return 0;
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+ }
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+
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+ temp = kzalloc(sizeof(struct drm_msm_dem_cfg), GFP_KERNEL);
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+ if (!temp)
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+ return -ENOMEM;
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+
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+ for (i = 0; i < ARRAY_SIZE(dcfg->cfg01_param0); i += 2) {
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+ temp[i >> 1] = (dcfg->cfg01_param0[i] & REG_MASK(12)) |
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+ ((dcfg->cfg01_param0[i + 1] & REG_MASK(12)) << 16);
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+ DRM_DEBUG_DRIVER("0x1c: index %d value %x\n", i >> 1,
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+ temp[i >> 1]);
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+ }
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x1c,
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+ temp, sizeof(u32) * 4, REG_BLK_WRITE_SINGLE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x1c: write err %d len %zd buffer index %d\n",
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+ rc, sizeof(u32) * 4, dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ memset(temp, 0, ARRAY_SIZE(dcfg->cfg0_param1));
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+ for (i = 0; i < ARRAY_SIZE(dcfg->cfg0_param1); i++) {
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+ p = (i < 4) ? &temp[0] : &temp[1];
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+ shift = (8 * i) % 32;
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+ *p |= (((dcfg->cfg0_param1[i] & 0x3f) & REG_MASK(6)) << shift);
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+ DRM_DEBUG_DRIVER("0xc: index %d value %x val %x shift %d\n",
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+ i, *p, (dcfg->cfg0_param1[i] & 0x3f), shift);
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+ }
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0xc,
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+ temp, sizeof(u32) * 2, REG_BLK_WRITE_SINGLE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0xc: write err %d len %zd buffer index %d\n",
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+ rc, sizeof(u32) * 2, dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ for (i = 0; i < ARRAY_SIZE(dcfg->cfg0_param0); i++)
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+ DRM_DEBUG_DRIVER("0x2c: index %d value %x\n",
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+ i, dcfg->cfg0_param0[i]);
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x2c,
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+ dcfg->cfg0_param0, ARRAY_SIZE(dcfg->cfg0_param0) * sizeof(u32),
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+ REG_BLK_WRITE_SINGLE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x2c: write err %d len %zd buf idx %d\n",
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+ rc, ARRAY_SIZE(dcfg->cfg0_param0) * sizeof(u32),
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+ dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ shift = 0;
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+ memset(temp, 0, ARRAY_SIZE(dcfg->cfg0_param3_c0) * 3 * sizeof(u32));
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+ for (i = 0; i < ARRAY_SIZE(dcfg->cfg0_param3_c0); i += 4) {
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+ temp[shift] = (dcfg->cfg0_param3_c0[i] & REG_MASK(8)) |
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+ (dcfg->cfg0_param3_c0[i + 1] & REG_MASK(8) << 8) |
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+ (dcfg->cfg0_param3_c0[i + 2] & REG_MASK(8) << 16) |
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+ (dcfg->cfg0_param3_c0[i + 3] & REG_MASK(8) << 23);
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+ temp[shift + 2] = (dcfg->cfg0_param3_c1[i] & REG_MASK(8)) |
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+ (dcfg->cfg0_param3_c1[i + 1] & REG_MASK(8) << 8) |
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+ (dcfg->cfg0_param3_c1[i + 2] & REG_MASK(8) << 16) |
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+ (dcfg->cfg0_param3_c1[i + 3] & REG_MASK(8) << 23);
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+ temp[shift + 4] = (dcfg->cfg0_param3_c2[i] & REG_MASK(8)) |
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+ (dcfg->cfg0_param3_c2[i + 1] & REG_MASK(8) << 8) |
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+ (dcfg->cfg0_param3_c2[i + 2] & REG_MASK(8) << 16) |
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+ (dcfg->cfg0_param3_c2[i + 3] & REG_MASK(8) << 23);
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+ DRM_DEBUG_DRIVER("0xb0: index %d value %x\n",
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+ shift, temp[shift]);
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+ DRM_DEBUG_DRIVER("0xb0: index %d value %x\n",
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+ shift + 2, temp[shift + 2]);
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+ DRM_DEBUG_DRIVER("0xb0: index %d value %x\n",
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+ shift + 4, temp[shift + 4]);
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+ shift++;
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+ }
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0xb0,
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+ temp, ARRAY_SIZE(dcfg->cfg0_param3_c0) * 3 * sizeof(u32),
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+ REG_BLK_WRITE_SINGLE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0xb0: write err %d len %zd buffer index %d\n", rc,
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+ ARRAY_SIZE(dcfg->cfg0_param3_c0) * 3 * sizeof(u32),
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+ dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ for (i = 0; i < 3; i++) {
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+ rc = __reg_dmav1_setup_demurav1_cfg0_c_params(dma_write_cfg,
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+ dcfg, dma_ops, temp,
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+ sizeof(struct drm_msm_dem_cfg), i,
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+ demura_base);
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+ if (rc)
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+ goto quit;
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+ }
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+
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+ width = hw_cfg->displayh >> 1;
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+ DRM_DEBUG_DRIVER("0x80: value %x\n", width);
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x80,
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+ &width, sizeof(width), REG_SINGLE_WRITE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x80: REG_SINGLE_WRITE err %d len %zd buf idx %d\n",
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+ rc, sizeof(width), dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ i = 0x400;
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0xe0,
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+ &i, sizeof(i), REG_SINGLE_WRITE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0xe0: REG_SINGLE_WRITE err %d len %zd buf idx %d\n",
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+ rc, sizeof(i), dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+
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+ memset(temp, 0, sizeof(u32) * 2);
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+ for (i = 0; i < ARRAY_SIZE(dcfg->cfg0_param4); i++)
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+ DRM_DEBUG_DRIVER("hfc gain is %d\n", dcfg->cfg0_param4[i]);
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+ temp[0] = (dcfg->cfg0_param4[0] & REG_MASK(5)) |
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+ ((dcfg->cfg0_param4[1] & REG_MASK(5)) << 8) |
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+ ((dcfg->cfg0_param4[2] & REG_MASK(5)) << 16) |
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+ ((dcfg->cfg0_param4[3] & REG_MASK(5)) << 24);
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+ temp[1] = (dcfg->cfg0_param4[4] & REG_MASK(5)) |
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+ ((dcfg->cfg0_param4[5] & REG_MASK(5)) << 8) |
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+ ((dcfg->cfg0_param4[6] & REG_MASK(5)) << 16) |
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+ ((dcfg->cfg0_param4[7] & REG_MASK(5)) << 24);
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+ DRM_DEBUG_DRIVER("0x4c: value is temp[0] %x temp[1] %x\n",
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+ temp[0], temp[1]);
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+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x4c,
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+ temp, sizeof(u32) * 2, REG_BLK_WRITE_SINGLE, 0, 0, 0);
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+ rc = dma_ops->setup_payload(dma_write_cfg);
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+ if (rc) {
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+ DRM_ERROR("0x4c: REG_BLK_WRITE_SINGLE %d len %zd buf idx %d\n",
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+ rc, sizeof(u32) * 2, dma_write_cfg->dma_buf->index);
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+ goto quit;
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+ }
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+quit:
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+ kfree(temp);
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+ return rc;
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+}
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+
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+static int __reg_dmav1_setup_demurav1_cfg1(struct sde_hw_dspp *ctx,
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+ struct drm_msm_dem_cfg *dcfg,
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+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
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+ struct sde_hw_reg_dma_ops *dma_ops,
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+ struct sde_hw_cp_cfg *hw_cfg)
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+{
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+ u32 temp[2], i, shift, *cfg1_data = NULL, len = 0;
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+ int rc;
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+ u32 width = 0;
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+ u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
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+
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+ if (!dcfg->cfg1_en) {
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+ DRM_DEBUG_DRIVER("dcfg->cfg1_en is disabled\n");
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+ return 0;
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+ }
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+ len = ARRAY_SIZE(dcfg->cfg1_param0_c0);
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+ cfg1_data = kcalloc(len, sizeof(u32), GFP_KERNEL);
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+ if (!cfg1_data)
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+ return -ENOMEM;
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+
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+ DRM_DEBUG_DRIVER("dcfg->cfg1_high_idx %d dcfg->cfg1_low_idx %d\n",
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+ dcfg->cfg1_high_idx, dcfg->cfg1_low_idx);
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+ if (dcfg->cfg1_high_idx >= ARRAY_SIZE(dcfg->cfg01_param0))
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+ dcfg->cfg1_high_idx = ARRAY_SIZE(dcfg->cfg01_param0) - 1;
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+
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+ if (dcfg->cfg1_low_idx >= ARRAY_SIZE(dcfg->cfg01_param0))
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+ dcfg->cfg1_low_idx = ARRAY_SIZE(dcfg->cfg01_param0) - 1;
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+
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+ temp[0] = dcfg->cfg01_param0[dcfg->cfg1_high_idx];
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+ temp[1] = dcfg->cfg01_param0[dcfg->cfg1_low_idx];
|
|
|
+ if (temp[0] > temp[1])
|
|
|
+ shift = temp[0] - temp[1];
|
|
|
+ else
|
|
|
+ shift = 1;
|
|
|
+ i = (1 << 22) / shift;
|
|
|
+ DRM_DEBUG_DRIVER("0x14: value %x\n", i);
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x14,
|
|
|
+ &i, sizeof(i), REG_SINGLE_WRITE, 0, 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("0x14: REG_SINGLE_WRITE failed ret %d\n", rc);
|
|
|
+ goto quit;
|
|
|
+ }
|
|
|
+
|
|
|
+ width = hw_cfg->displayh;
|
|
|
+ DRM_DEBUG_DRIVER("width for LFC calculation is %d\n", width);
|
|
|
+ if (hw_cfg->displayh < hw_cfg->displayv) {
|
|
|
+ temp[0] = (8 * (1 << 21)) / width;
|
|
|
+ temp[1] = (16 * (1 << 21)) / hw_cfg->displayv;
|
|
|
+ } else {
|
|
|
+ temp[0] = (16 * (1 << 21)) / width;
|
|
|
+ temp[1] = (8 * (1 << 21)) / hw_cfg->displayv;
|
|
|
+ }
|
|
|
+ temp[0] = (dcfg->pentile) ? ((temp[0]) | BIT(31)) : temp[0];
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x54,
|
|
|
+ &temp[0], sizeof(temp[0]), REG_SINGLE_WRITE, 0, 0, 0);
|
|
|
+ DRM_DEBUG_DRIVER("0x54 value %x\n", temp[0]);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("0x54: REG_SINGLE_WRITE ret %d\n", rc);
|
|
|
+ goto quit;
|
|
|
+ }
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x5c,
|
|
|
+ &temp[1], sizeof(temp[1]), REG_SINGLE_WRITE, 0, 0, 0);
|
|
|
+ DRM_DEBUG_DRIVER("0x5c value %x\n", temp[1]);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("0x5c: REG_SINGLE_WRITE ret %d\n", rc);
|
|
|
+ goto quit;
|
|
|
+ }
|
|
|
+
|
|
|
+ cfg1_data[0] = (dcfg->cfg1_param0_c0[0] & REG_MASK(10)) |
|
|
|
+ ((dcfg->cfg1_param0_c1[0] & REG_MASK(10)) << 10) |
|
|
|
+ ((dcfg->cfg1_param0_c2[0] & REG_MASK(10)) << 20) | BIT(31);
|
|
|
+ DRM_DEBUG_DRIVER("0x64: value %x\n", cfg1_data[0]);
|
|
|
+ for (i = 1; i < len; i++) {
|
|
|
+ cfg1_data[i] = (dcfg->cfg1_param0_c0[i] & REG_MASK(10)) |
|
|
|
+ ((dcfg->cfg1_param0_c1[i] & REG_MASK(10)) << 10) |
|
|
|
+ ((dcfg->cfg1_param0_c2[i] & REG_MASK(10)) << 20);
|
|
|
+ DRM_DEBUG_DRIVER("0x64 index %d value %x\n", i,
|
|
|
+ cfg1_data[i]);
|
|
|
+ }
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x64,
|
|
|
+ cfg1_data, len * sizeof(u32), REG_BLK_WRITE_INC, 0,
|
|
|
+ 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("lut write failed ret %d\n", rc);
|
|
|
+ goto quit;
|
|
|
+ }
|
|
|
+
|
|
|
+quit:
|
|
|
+ kfree(cfg1_data);
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+static int __reg_dmav1_setup_demurav1_cfg3(struct sde_hw_dspp *ctx,
|
|
|
+ struct drm_msm_dem_cfg *dcfg,
|
|
|
+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
|
|
|
+ struct sde_hw_reg_dma_ops *dma_ops)
|
|
|
+{
|
|
|
+ u32 temp[CFG3_PARAM01_LEN + 1];
|
|
|
+ int rc, i;
|
|
|
+ u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
|
|
|
+
|
|
|
+ if (!dcfg->cfg3_en) {
|
|
|
+ DRM_DEBUG_DRIVER("dcfg->cfg3_en is disabled\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ temp[0] = dcfg->cfg3_param0_a[0] & REG_MASK(10);
|
|
|
+ temp[0] = (dcfg->cfg3_param0_a[1] & REG_MASK(10)) << 16;
|
|
|
+ temp[1] = dcfg->cfg3_param0_a[2] & REG_MASK(10);
|
|
|
+ temp[1] = (dcfg->cfg3_param0_a[3] & REG_MASK(10)) << 16;
|
|
|
+ temp[2] = dcfg->cfg3_param0_b[0] & REG_MASK(11);
|
|
|
+ temp[2] = (dcfg->cfg3_param0_b[1] & REG_MASK(11)) << 16;
|
|
|
+ temp[3] = dcfg->cfg3_param0_b[2] & REG_MASK(11);
|
|
|
+ temp[3] = (dcfg->cfg3_param0_b[3] & REG_MASK(11)) << 16;
|
|
|
+ temp[4] = (dcfg->cfg3_ab_adj) & REG_MASK(11);
|
|
|
+ for (i = 0; i < ARRAY_SIZE(temp); i++)
|
|
|
+ DRM_DEBUG_DRIVER("0xd0: index %i value %x\n", i, temp[i]);
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0xd0,
|
|
|
+ temp, ARRAY_SIZE(temp) * sizeof(u32), REG_BLK_WRITE_SINGLE, 0,
|
|
|
+ 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc)
|
|
|
+ DRM_ERROR("0xd0: REG_BLK_WRITE_SINGLE failed ret %d\n", rc);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+static int __reg_dmav1_setup_demurav1_cfg5(struct sde_hw_dspp *ctx,
|
|
|
+ struct drm_msm_dem_cfg *dcfg,
|
|
|
+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
|
|
|
+ struct sde_hw_reg_dma_ops *dma_ops)
|
|
|
+{
|
|
|
+ u32 temp[CFG5_PARAM01_LEN];
|
|
|
+ int rc, i;
|
|
|
+ u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
|
|
|
+
|
|
|
+ if (!dcfg->cfg5_en) {
|
|
|
+ DRM_DEBUG_DRIVER("dcfg->cfg5_en is disabled\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ temp[0] = dcfg->cfg5_param0[0] & REG_MASK(10);
|
|
|
+ temp[0] |= (dcfg->cfg5_param0[1] & REG_MASK(10)) << 16;
|
|
|
+ temp[1] = dcfg->cfg5_param0[2] & REG_MASK(10);
|
|
|
+ temp[1] |= (dcfg->cfg5_param0[3] & REG_MASK(10)) << 16;
|
|
|
+ temp[2] = dcfg->cfg5_param1[0] & REG_MASK(11);
|
|
|
+ temp[2] |= (dcfg->cfg5_param1[1] & REG_MASK(11)) << 16;
|
|
|
+ temp[3] = dcfg->cfg5_param1[2] & REG_MASK(11);
|
|
|
+ temp[3] |= (dcfg->cfg5_param1[3] & REG_MASK(11)) << 16;
|
|
|
+ for (i = 0; i < ARRAY_SIZE(temp); i++)
|
|
|
+ DRM_DEBUG_DRIVER("0xa0: index %i value %x\n", i, temp[i]);
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0xa0,
|
|
|
+ temp, ARRAY_SIZE(temp) * sizeof(u32), REG_BLK_WRITE_SINGLE, 0,
|
|
|
+ 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc)
|
|
|
+ DRM_ERROR("0xa0: REG_BLK_WRITE_SINGLE failed ret %d\n", rc);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static int __reg_dmav1_setup_demurav1_en(struct sde_hw_dspp *ctx,
|
|
|
+ struct drm_msm_dem_cfg *dcfg,
|
|
|
+ struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
|
|
|
+ struct sde_hw_reg_dma_ops *dma_ops)
|
|
|
+{
|
|
|
+ u32 en = 0, backl;
|
|
|
+ int rc;
|
|
|
+ u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
|
|
|
+
|
|
|
+ backl = (1024 << 16) | 1024;
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x8,
|
|
|
+ &backl, sizeof(backl), REG_SINGLE_WRITE, 0, 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("0x8: REG_SINGLE_WRITE failed ret %d\n", rc);
|
|
|
+ return rc;
|
|
|
+ }
|
|
|
+
|
|
|
+ en = (dcfg->src_id) ? BIT(31) : 0;
|
|
|
+ en |= (dcfg->cfg1_high_idx & REG_MASK(3)) << 24;
|
|
|
+ en |= (dcfg->cfg1_low_idx & REG_MASK(3)) << 20;
|
|
|
+ en |= (dcfg->c2_depth & REG_MASK(4)) << 16;
|
|
|
+ en |= (dcfg->c1_depth & REG_MASK(4)) << 12;
|
|
|
+ en |= (dcfg->c0_depth & REG_MASK(4)) << 8;
|
|
|
+ en |= (dcfg->cfg3_en) ? BIT(5) : 0;
|
|
|
+ en |= (dcfg->cfg4_en) ? BIT(4) : 0;
|
|
|
+ en |= (dcfg->cfg2_en) ? BIT(3) : 0;
|
|
|
+ en |= (dcfg->cfg0_en) ? BIT(2) : 0;
|
|
|
+ en |= (dcfg->cfg1_en) ? BIT(1) : 0;
|
|
|
+ DRM_DEBUG_DRIVER("demura en %x\n", en);
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x4,
|
|
|
+ &en, sizeof(en), REG_SINGLE_WRITE, 0, 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(dma_write_cfg);
|
|
|
+ if (rc)
|
|
|
+ DRM_ERROR("0x4: REG_SINGLE_WRITE failed ret %d\n", rc);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+void reg_dmav1_setup_demurav1(struct sde_hw_dspp *ctx, void *cfx)
|
|
|
+{
|
|
|
+ struct drm_msm_dem_cfg *dcfg;
|
|
|
+ struct sde_hw_cp_cfg *hw_cfg = cfx;
|
|
|
+ int rc = 0;
|
|
|
+ struct sde_hw_reg_dma_ops *dma_ops;
|
|
|
+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
|
|
|
+ struct sde_reg_dma_kickoff_cfg kick_off;
|
|
|
+
|
|
|
+ rc = reg_dma_dspp_check(ctx, cfx, DEMURA_CFG);
|
|
|
+ if (rc)
|
|
|
+ return;
|
|
|
+
|
|
|
+ if (!hw_cfg->payload) {
|
|
|
+ reg_dma_demura_off(ctx, hw_cfg);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (hw_cfg->len != sizeof(struct drm_msm_dem_cfg)) {
|
|
|
+ DRM_ERROR("invalid sz of payload len %d exp %zd\n",
|
|
|
+ hw_cfg->len, sizeof(struct drm_msm_dem_cfg));
|
|
|
+ }
|
|
|
+ dcfg = hw_cfg->payload;
|
|
|
+ dma_ops = sde_reg_dma_get_ops();
|
|
|
+ dma_ops->reset_reg_dma_buf(dspp_buf[DEMURA_CFG][ctx->idx]);
|
|
|
+
|
|
|
+ REG_DMA_INIT_OPS(dma_write_cfg, MDSS, DEMURA_CFG,
|
|
|
+ dspp_buf[DEMURA_CFG][ctx->idx]);
|
|
|
+
|
|
|
+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
|
|
|
+ rc = dma_ops->setup_payload(&dma_write_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("write decode select failed ret %d\n", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ rc = __reg_dmav1_setup_demurav1_cfg0(ctx, dcfg, &dma_write_cfg,
|
|
|
+ dma_ops, hw_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("failed setup_demurav1_cfg0 rc %d", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ rc = __reg_dmav1_setup_demurav1_cfg1(ctx, dcfg, &dma_write_cfg,
|
|
|
+ dma_ops, hw_cfg);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("failed setup_demurav1_cfg1 rc %d", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ rc = __reg_dmav1_setup_demurav1_cfg3(ctx, dcfg, &dma_write_cfg,
|
|
|
+ dma_ops);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("failed setup_demurav1_cfg3 rc %d", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ rc = __reg_dmav1_setup_demurav1_cfg5(ctx, dcfg, &dma_write_cfg,
|
|
|
+ dma_ops);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("failed setup_demurav1_cfg5 rc %d", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ rc = __reg_dmav1_setup_demurav1_en(ctx, dcfg, &dma_write_cfg,
|
|
|
+ dma_ops);
|
|
|
+ if (rc) {
|
|
|
+ DRM_ERROR("failed setup_demurav1_en rc %d", rc);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
|
|
|
+ dspp_buf[DEMURA_CFG][ctx->idx],
|
|
|
+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
|
|
|
+
|
|
|
+ DRM_DEBUG("enable demura buffer size %d\n",
|
|
|
+ dspp_buf[DEMURA_CFG][ctx->idx]->index);
|
|
|
+
|
|
|
+ rc = dma_ops->kick_off(&kick_off);
|
|
|
+ if (rc)
|
|
|
+ DRM_ERROR("failed to kick off ret %d\n", rc);
|
|
|
+
|
|
|
+}
|
qctecmdr