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@@ -62,8 +62,19 @@
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#define DCE_SEL 0x450
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-#define ROT_SID_RD 0x20
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-#define ROT_SID_WR 0x24
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+#define MDP_SID_VIG0 0x0
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+#define MDP_SID_VIG1 0x4
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+#define MDP_SID_VIG2 0x8
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+#define MDP_SID_VIG3 0xC
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+#define MDP_SID_DMA0 0x10
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+#define MDP_SID_DMA1 0x14
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+#define MDP_SID_DMA2 0x18
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+#define MDP_SID_DMA3 0x1C
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+#define MDP_SID_ROT_RD 0x20
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+#define MDP_SID_ROT_WR 0x24
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+#define MDP_SID_WB2 0x28
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+#define MDP_SID_XIN7 0x2C
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+
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#define ROT_SID_ID_VAL 0x1c
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static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
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@@ -470,10 +481,38 @@ struct sde_hw_sid *sde_hw_sid_init(void __iomem *addr,
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return c;
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}
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-void sde_hw_sid_rotator_set(struct sde_hw_sid *sid)
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+void sde_hw_set_rotator_sid(struct sde_hw_sid *sid)
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{
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- SDE_REG_WRITE(&sid->hw, ROT_SID_RD, ROT_SID_ID_VAL);
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- SDE_REG_WRITE(&sid->hw, ROT_SID_WR, ROT_SID_ID_VAL);
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+ if (!sid)
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+ return;
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+
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+ SDE_REG_WRITE(&sid->hw, MDP_SID_ROT_RD, ROT_SID_ID_VAL);
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+ SDE_REG_WRITE(&sid->hw, MDP_SID_ROT_WR, ROT_SID_ID_VAL);
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+}
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+
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+void sde_hw_set_sspp_sid(struct sde_hw_sid *sid, u32 pipe, u32 vm)
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+{
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+ u32 offset = 0;
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+
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+ if (!sid)
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+ return;
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+
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+ if ((pipe >= SSPP_VIG0) && (pipe <= SSPP_VIG3))
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+ offset = MDP_SID_VIG0 + ((pipe - SSPP_VIG0) * 4);
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+ else if ((pipe >= SSPP_DMA0) && (pipe <= SSPP_DMA3))
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+ offset = MDP_SID_DMA0 + ((pipe - SSPP_DMA0) * 4);
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+ else
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+ return;
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+
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+ SDE_REG_WRITE(&sid->hw, offset, vm << 2);
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+}
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+
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+void sde_hw_set_lutdma_sid(struct sde_hw_sid *sid, u32 vm)
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+{
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+ if (!sid)
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+ return;
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+
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+ SDE_REG_WRITE(&sid->hw, MDP_SID_XIN7, vm << 2);
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}
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static void sde_hw_program_cwb_ppb_ctrl(struct sde_hw_mdp *mdp,
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