This change sets lm_mask for dp connector based on
number of LMs allocated by RM. This mask will be
used during rm allocation and validation of dcwb
mixers for dp display.
Change-Id: I271af03da560587faf17446471bd6b81bb9e809b
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change corrects the conditional check in commit 2859b760a414
("disp: msm: sde: proper allocation of dcwb for LMs") with respect
to DCWB mixer allocation in RM.
Change-Id: I83fd39ed366774f20046b8f9c0e6959116b541ee
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During dcwb mixer allocation, resource manager allocates
the first available mixer in the free list. In dual display
uses case with 1 1 1 topology if only secondary is running
CWB then, resource manager allocates DCWB0 which leads to wb
timeout due to HW does not have the connection between LM1
and DCWB0. This change allocates proper dcwb for the LMs in RM.
Change-Id: I0c8b04b46ccad5a7d7dd591fbfa3ea0915eccdc6
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
When cwb is triggered on built-in display secondary display
with (1,1,1) topology, improper dcwb_idx value is passed
to pp_dither and CTL registers. This change populates proper
dcwb_idx during pp block dt parsing and passes the same for
programming.
Change-Id: I543eede6f5fd9c2c80799503e3639ea9e89058ca
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change updates atomic check for VM_ACQUIRE transition
only for android VM since in trusted VM, vm_owns_hw is
updated asynchronously. This change fixes atomic check
failures seen with commit ea9696a769d3 ("disp: msm: sde:
update atomic check for VM_REQ_ACQUIRE state").
Change-Id: I951e41490c01b543b591c0bbe2700fd8eea39c78
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
The pages backing the GEM objects are kept pinned in place as
long as they are alive, so they must not be allocated from the
MOVABLE zone. Blocking page migration for too long will cause
the VM subsystem headaches and will outright break CMA, as a
few pinned pages in CMA will lead to failure to find the
required large contiguous regions.
Change-Id: I5eba32fc8a2730eac29668dbd96aaf8f04ac155f
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Git-commit: 0abdba47dc1df708c365421d481734d3f7fecb01
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change adds a wait for input spec fence to bind
before registering for hw fencing wait on it.
Change-Id: I5453547c29672e39a95b91197983075e3b61d1eb
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Add tx wait for WB display during modeset to avoid unbalanced
IRQ handle.
Change-Id: I18337e2a06fe5ec98d4d6e6d766abbf4ec585703
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
This change depends on HAL change which sets CONNECTOR_SET_CRTC
property to null for cwb conn, if cwb is enabled during esd failures.
This causes power off commit crtc_state's active_changed and
connectors_changed set to true, which is causing seamless_crtc
to true during msm_disable_outputs and this leads to invalid crtc
state. This change modifies the seamless_crtc condition and
the msm_crtc_set_mode callback is early returned during such cases
to power off crtc.
Without this change, crtc_disable is not called which avoids
SDE_FENCE_RESET_TIMELINE. On esd failure release fence is not
signaled for the planes used in the composition and this further
leads to GPU wait on release fence and causes fence timeout.
Change-Id: Ie5d8f1b99d6a2d335330331288223fbeba9f6e64
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
In case of dual dsi usecase, since both the encoders use
the same CTL path, this change ensures that uidle ctl
settings are updated only by the master encoder.
Change-Id: Ic47703aeee69999b4535034b5cd7a65cf53cd0fb
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Adjust the data width calculation to reduce the rounding off error
when the widebus is enabled.
Change-Id: Ia2fa4536ce519548989e2befcb22fb685f286c9e
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
The sequence during which issue is observed:
1) wb pending_retire_fence_cnt is equal to 2 due to which
it waits for WB_DONE irq. Current pending_retire_fence_cnt
is 2 and required pending_retire_fence_cnt is 1.
2) Due to external reasons, irq's are disabled and after
some duration, back to back irq's are received.
3) Because of this, pending_retire_fence_cnt becomes zero
before the commit thread could wakeup and validate the
condition.
sde_encoder_helper_wait_for_irq API will wait for complete
timeout due to the count mismatch. This change adds
required check to early exit in such usecases.
Change-Id: I4f9c817cc7acee17424b77928d34b039afcaeae5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
CTL datapath idx can be switched between secondary and external displays
as per current SW code. This change avoids the clearing the SW flush ctx
in prepare_commit during resume use case. It fixes the GPU fence timeouts
seen during below scenario.
Issue scenario:
1. Primary display was using CTL_0 and it is reserved.
2. Secondary display was using CTL_1 and suspend occurred.
CTL_1 is added to RM free list.
3. When external Display is connected, it starts using CTL_1
datapath.
4. Secondary display is resumed and it starts using CTL_2.
During prepare_commit, phys_enc->hw_ctl was CTL_1 and
SW is clearing the flush ctx of external Display.
5. Since CTL_1 flush bits are cleared, SW is not programming the
CTL_FLUSH register for this composition and release/retire fences
are not signaled causing fence timeouts at GPU end and Input fence
timeout at display end finally leading to SF hung.
Change-Id: Ic843ce5c4f06f1620636abd24d443952c2ba8dc5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Following is the sequence during which issue is observed:
1) HAL sends a commit with VM_REQ_RELEASE property set
indicating transition from primary vm to trusted vm.
2) Before the transition commit ends, there is atomic check
for next commit from HAL with VM_REQ_ACQUIRE property
indicating transition from trusted vm to primary vm.
3) Since the HW is currently owned by the primary vm, it
performs a early return during check phase. After this,
transition has occurred from primary to trusted and when
the next commit is scheduled on primary, it results in
crash since it is currently not the owner.
This change adds necessary to check avoid commit with
VM_REQ_ACQUIRE state before the transition.
Change-Id: I4650305a95ef6bc495375a21a799522e67a61883
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
DSC enable status is updated in DP panel struct as per the DPCD reg
read which is done at the start of the HPD ISR. However, there is a
chance that DSC is actually disabled later during mode query due to
shortage of DSC blocks. This status is stored as part of compression
info structure. This change checks for the latter struct to determine
the actual DSC status.
Change-Id: Id7cd4e65060f2ec939f945e9ac4f4e66260605d3
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change detects if a encoder has a CTL datapath allocated
and Resource manager is allocating a different CTL block and
avoids this switch. If the CTL datapath switch is allowed, pp_done
timeouts are seen in HW. The reason is due to crossbar is confused
due to the "XSEL" values that are present in previous CTL_*_LAYER_* are
not cleared and SW needs to issue a NULL db update to reset these
"XSEL" values when switching the CTL path.
Change-Id: Iee70c7ddb06feb5cea6dc9f147a942f80c48a7da
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change moves the SMMU context bank not found log from error
to debug as some of the context-banks like nrt-sec/nrt-unsec
are expected to be not available for most of the targets.
Change-Id: If60e83ae8088a484b4ea02f527ce2a8f43573e17
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
The hs timer control settings can't match with dsi data transfer
requirement, so it may lead to timeout issue when running into low
frame rate, update this change to fix such issue for 30hz display
mode.
Change-Id: I01942a494f46e0023061a9d307a9d2ca1fd8159a
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
DCS commands are not supported on DP displays, thus there is
no need to wait for active region to start before triggering
a DCS command which can cause additional latency during power
ON use case.
This change skips the active region wait for non DSI panels.
Change-Id: I50c6b808f839468bda74b13d7a75e8410d81dd0d
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add existing debug logs to ipc logging to be
accessed through debugfs.
Change-Id: Id9bfe61cb7921674eadc5635847c81a0fbdaef5c
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
When destination scaler feature is enabled along with demura,
the crtc w/h will be lesser than the deumra layer w/h as it is
based on the panel w/h. Remove the invalid validation of
demura layers against crtc w/h to allow this usecase.
Change-Id: I5afd0407382a1bce458c97fcf8d571f5e7c0774f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
If LFC of demura is disabled, there are few parameters that needs to be
set in demura hardware block. Change ensures that the mandatory params
are set.
Change-Id: Ia2b7d80ccc60c19b7106ed417e7803a205bef6ff
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
pll_codes_region is not defined on TVM and not programmed.
So, adding TVM check to avoid parsing pll code data.
Change-Id: Ia6280ca3fc1b19866673a6767de465d17681add7
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add bound check for number of dnsc_blur blocks, while parsing from
device tree. Fix out of bound access while setting the llcc_active
during system cache disable case in writeback.
Change-Id: I7e604db5ebfaa6e8b6f066e0f6efb76e7d78e604
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change provides required support to disable display module
compilation along with all modules and supports module specific
override to enable compilation if required.
Change-Id: I38acdce4083e38245eb6285c99d5dbbd15911fbb
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
