disp: msm: sde: avoid clear_pending_flush on hw_ctl during power_on commit

CTL datapath idx can be switched between secondary and external displays
as per current SW code. This change avoids the clearing the SW flush ctx
in prepare_commit during resume use case. It fixes the GPU fence timeouts
seen during below scenario.
Issue scenario:
1. Primary display was using CTL_0 and it is reserved.
2. Secondary display was using CTL_1 and suspend occurred.
   CTL_1 is added to RM free list.
3. When external Display is connected, it starts using CTL_1
   datapath.
4. Secondary display is resumed and it starts using CTL_2.
   During prepare_commit, phys_enc->hw_ctl was CTL_1 and
   SW is clearing the flush ctx of external Display.
5. Since CTL_1 flush bits are cleared, SW is not programming the
   CTL_FLUSH register for this composition and release/retire fences
   are not signaled causing fence timeouts at GPU end and Input fence
   timeout at display end finally leading to SF hung.

Change-Id: Ic843ce5c4f06f1620636abd24d443952c2ba8dc5
Signed-off-by: Jayaprakash Madisetty <[email protected]>

msm/sde/sde_encoder.c

@@ -3167,6 +3167,7 @@ void sde_encoder_virt_reset(struct drm_encoder *drm_enc)
 		if (sde_enc->phys_encs[i]) {
 			sde_enc->phys_encs[i]->cont_splash_enabled = false;
 			sde_enc->phys_encs[i]->connector = NULL;
+			sde_enc->phys_encs[i]->hw_ctl = NULL;
 		}
 		atomic_set(&sde_enc->frame_done_cnt[i], 0);
 	}

msm/sde/sde_plane.c

@@ -650,7 +650,10 @@ int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
 				break;
 			}
 
-			SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
+			if (ret)
+				SDE_EVT32(DRMID(plane), -ret, prefix, SDE_EVTLOG_ERROR);
+			else
+				SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
 		} else {
 			ret = 0;
 		}