drm: msm: update lfc config for demura

If LFC of demura is disabled, there are few parameters that needs to be
set in demura hardware block. Change ensures that the mandatory params
are set.

Change-Id: Ia2b7d80ccc60c19b7106ed417e7803a205bef6ff
Signed-off-by: Gopikrishnaiah Anandan <[email protected]>

msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -5467,10 +5467,6 @@ static int __reg_dmav1_setup_demurav1_cfg1(struct sde_hw_dspp *ctx,
 	u32 width = 0;
 	u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
 
-	if (!dcfg->cfg1_en) {
-		DRM_DEBUG_DRIVER("dcfg->cfg1_en is disabled\n");
-		return 0;
-	}
 	len = ARRAY_SIZE(dcfg->cfg1_param0_c0);
 	cfg1_data = kvzalloc((len * sizeof(u32)), GFP_KERNEL);
 	if (!cfg1_data)
@@ -5529,24 +5525,26 @@ static int __reg_dmav1_setup_demurav1_cfg1(struct sde_hw_dspp *ctx,
 		goto quit;
 	}
 
-	cfg1_data[0] = (dcfg->cfg1_param0_c0[0] & REG_MASK(10)) |
-		((dcfg->cfg1_param0_c1[0] & REG_MASK(10)) << 10) |
-		((dcfg->cfg1_param0_c2[0] & REG_MASK(10)) << 20) | BIT(31);
-	DRM_DEBUG_DRIVER("0x64: value %x\n", cfg1_data[0]);
-	for (i = 1; i < len; i++) {
-		cfg1_data[i] = (dcfg->cfg1_param0_c0[i] & REG_MASK(10)) |
-			((dcfg->cfg1_param0_c1[i] & REG_MASK(10)) << 10) |
-			((dcfg->cfg1_param0_c2[i] & REG_MASK(10)) << 20);
-			DRM_DEBUG_DRIVER("0x64 index %d value %x\n", i,
-					cfg1_data[i]);
-	}
-	REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x64,
-		cfg1_data, len * sizeof(u32), REG_BLK_WRITE_INC, 0,
-		0, 0);
-	rc = dma_ops->setup_payload(dma_write_cfg);
-	if (rc) {
-		DRM_ERROR("lut write failed ret %d\n", rc);
-		goto quit;
+	if (dcfg->cfg1_en) {
+		cfg1_data[0] = (dcfg->cfg1_param0_c0[0] & REG_MASK(10)) |
+			((dcfg->cfg1_param0_c1[0] & REG_MASK(10)) << 10) |
+			((dcfg->cfg1_param0_c2[0] & REG_MASK(10)) << 20) | BIT(31);
+		DRM_DEBUG_DRIVER("0x64: value %x\n", cfg1_data[0]);
+		for (i = 1; i < len; i++) {
+			cfg1_data[i] = (dcfg->cfg1_param0_c0[i] & REG_MASK(10)) |
+				((dcfg->cfg1_param0_c1[i] & REG_MASK(10)) << 10) |
+				((dcfg->cfg1_param0_c2[i] & REG_MASK(10)) << 20);
+				DRM_DEBUG_DRIVER("0x64 index %d value %x\n", i,
+						cfg1_data[i]);
+		}
+		REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x64,
+			cfg1_data, len * sizeof(u32), REG_BLK_WRITE_INC, 0,
+			0, 0);
+		rc = dma_ops->setup_payload(dma_write_cfg);
+		if (rc) {
+			DRM_ERROR("lut write failed ret %d\n", rc);
+			goto quit;
+		}
 	}
 
 quit: