Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
In non-qsync panels when min FPS is not published in DT,
the default min fps is set to 10 FPS. This change handles mode
switch cases, when panel FPS drops below 10 FPS by updating
min FPS to panel FPS for Expected Present Time calculations.
As part of the change, reduce 2ms from EPT to account for
scheduling delays after schedule_timeout.
Change-Id: Idc206f39adfb3517b4ea2cfa303fe53182a8e63e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
With DP plug-ins, it is possible for the connector fill modes API
to be called to update available modes on the connector and at the
same time have the commit thread calculate the max mode width
on the available modes. As a result, it is possible to access
pruned modes from the modelist.
This change moves the calculation into the fill modes call-flow,
so that the max mode width is determined once, and stored to be
used during virt enable.
Change-Id: I6c332c57e6e98ed98444a303add97d163a2031bf
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
PPB size programming checks for the max horizontal width of the
panel by checking all available modes. In some DP usecases,
it is possible that this information is not ready at this point.
However, this is not an error, as by default driver will set the
maximum size.
This change reduces the error log to a debug warning.
Change-Id: Ieb63524457db410a2569682f2c3863e082c60805
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
MDSS 10.0 onwards, hw supports programming of pingpong
latency buffer size based on the resolution of display.
In prior targets full size of the latency buffer is used.
This change adds required support in sde driver to program
the pingpong buffer size based on systems recommended
latency lines requirement and the display resolution.
Change-Id: I172b19e5b397eb86190de57fed36f24cd67d2207
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Introduce a new connector property called “EPT_FPS” for the cmd
mode panels. User space will set the “EPT_FPS” based on the
intended content fps, relative to the last retire fence timestamp
as calculated by Surface flinger. Program start window based
on the Expected Present Time fps.
Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Time the flush bit setting to match with the expected frame
rate. To achieve this, introduce a new connector property called
“Expected_Present_Time”. User space will set it based on the
intended content fps and AVR step, relative to the last retire
fence timestamp as calculated by user space. Delay the frame
trigger to match with the EPT.
Change-Id: I0b86caaa53ee2e37671167acdffd22ec62b4e9ae
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Timing DB needs to be disabled after panel vnsyc.
Update the wait time to reflect difference in line time
between MDP and panel vsync.
Change-Id: Ib5282d67995e8379ead928218f31a8f9fe7fa978
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change adds support for dynamically enabling and disabling
additional physical encoder IRQs.
Change-Id: I500fa69d1b8b8df39fd608391c906257efdea63b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
As per DP HPG recommendation, controller flush mode is
set to be synchronous with a vsync. This requires a
peripheral flush to be issued for HDR SDP to be processed.
Currently in a static HDR use case, since the peripheral
flush is not issued after queueing an HDR SDP, it never
gets sent to the sink and it stays in SDR mode. This change
issues a peripheral flush on every DP commit, so that
any pending SDPs are flushed.
Change-Id: I0ed82b6cd8df33539a3067c6ad9827f74de2ed51
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Fix debug message arguments in sde which are found with
-Wformat-extra-args and -Wstrict-prototypes compilation
flag and add compile flags to msm compilation.
Change-Id: Ic7f30e0cab3ea16b7f2a34658262b6f51da259e9
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Pass sde_enc to sde_encoder_control_te instead of drm_enc,
as all callers have access to sde_enc.
Change-Id: Ic61b78c9e8d1ab2ed6e371c19a72367efbb6e5ee
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.
Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).
This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.
Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.
Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Pineapple target adds support for writeback contributing to
fal status. This removes the need to signal fal10 veto in those
usecases. In addition, it is no longer needed to program uidle
active per ctl path.
Change-Id: I5e3509fa6399d212563322d51eba04c38a41e9b8
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.
Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
In the current code if there is a switch from DSC to non-DSC
mode, all the DSC blocks attached to the sde_encoder are not
cleaned up properly. Due to this, during virt disable these
DSC blocks are disabled and flushed resulting in underruns
on other ctl paths which might be using them. This change
properly cleans up all the dsc/vdc attached to the sde
encoder to avoid such issues.
Change-Id: Ie644701cbda6b4d056bc7ef30300be96096c5214
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Enable the clks/irqs & update RSC state during encoder disable.
This ensures RSC is in correct state during the non-primary disable
commit as it might have entered idle power collapse before the
disable.
Change-Id: Idf82efb3a7bc895e1a97c6cdeeb62970184c8e5d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add tx wait for WB display during modeset to avoid unbalanced
IRQ handle.
Change-Id: I18337e2a06fe5ec98d4d6e6d766abbf4ec585703
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
In case of dual dsi usecase, since both the encoders use
the same CTL path, this change ensures that uidle ctl
settings are updated only by the master encoder.
Change-Id: Ic47703aeee69999b4535034b5cd7a65cf53cd0fb
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
The sequence during which issue is observed:
1) wb pending_retire_fence_cnt is equal to 2 due to which
it waits for WB_DONE irq. Current pending_retire_fence_cnt
is 2 and required pending_retire_fence_cnt is 1.
2) Due to external reasons, irq's are disabled and after
some duration, back to back irq's are received.
3) Because of this, pending_retire_fence_cnt becomes zero
before the commit thread could wakeup and validate the
condition.
sde_encoder_helper_wait_for_irq API will wait for complete
timeout due to the count mismatch. This change adds
required check to early exit in such usecases.
Change-Id: I4f9c817cc7acee17424b77928d34b039afcaeae5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
CTL datapath idx can be switched between secondary and external displays
as per current SW code. This change avoids the clearing the SW flush ctx
in prepare_commit during resume use case. It fixes the GPU fence timeouts
seen during below scenario.
Issue scenario:
1. Primary display was using CTL_0 and it is reserved.
2. Secondary display was using CTL_1 and suspend occurred.
CTL_1 is added to RM free list.
3. When external Display is connected, it starts using CTL_1
datapath.
4. Secondary display is resumed and it starts using CTL_2.
During prepare_commit, phys_enc->hw_ctl was CTL_1 and
SW is clearing the flush ctx of external Display.
5. Since CTL_1 flush bits are cleared, SW is not programming the
CTL_FLUSH register for this composition and release/retire fences
are not signaled causing fence timeouts at GPU end and Input fence
timeout at display end finally leading to SF hung.
Change-Id: Ic843ce5c4f06f1620636abd24d443952c2ba8dc5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support display emulation targets on RUMI
This change does the following:
-parse dt node to enable display emulation mode.
-use sde_reg_read for pool timeout ops and debug fs dump.
-increases the kickoff timeout when emulation is enabled.
-bypass AXI halt operation when emulation is enabled.
Change-Id: Idc493964c0b8fc89f5d85fcc5755e0874a12d211
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.
Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
