提交線圖

69 次程式碼提交

作者 SHA1 備註 日期
qctecmdr
d1f804e2ac Merge "msm: ipa3: Changes to remove the CNTXT_SCRATCH_1 config" 2021-08-03 17:33:42 -07:00
Ashok Vuyyuru
3d2bf967c0 msm: ipa3: Changes to remove the CNTXT_SCRATCH_1 config
Context scratch 1 register configuration not required, So removing
these changes.

Change-Id: Ic72fc128fc6468e5844d10d9321a85a85c4ed60c
2021-08-03 00:01:19 +05:30
Michael Adisumarta
8e3953ea4e msm: ipa5: ipa_stats support for ipa_lnx_agent
Includes support for IPA stats to be able to send log packet
to ipa_lnx_agent and then to SPEARHEAD framework.

Change-Id: I3112fc6b2e66e15140f638bfff9905bba6997e46
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-07-20 13:44:23 -07:00
qctecmdr
76f2b86821 Merge "msm: gsi: Add debug code for Flow Control" 2021-05-20 18:08:58 -07:00
Sivan Reinstein
5b713d37b0 msm: gsi: Add debug code for Flow Control
Increase timeout while waiting for FC command to complete.
For enable FC command wait longer in case PENDING bit is set.

Change-Id: I6d4443b1688d2ae426079638216829a4ddb30d94
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-20 09:14:08 +03:00
qctecmdr
089976fc29 Merge "msm: ipa3: Changes to read the halt command return code after some delay" 2021-05-14 00:52:38 -07:00
Ashok Vuyyuru
797b181281 msm: ipa3: Changes to read the halt command return code after some delay
In some cases for updating the return code in SCRATCH register taking
time after raising the global interrupt. Adding changes to wait for
some time read the SCRATCH register again and also printing the
test bus registers and Q6 channel state in failed scenario.

Change-Id: I4112a2290739daa79629f718d9725258518aba4c
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-13 11:59:29 +05:30
Sivan Reinstein
2a9bd8f3af msm: ipa: Clear IEOB for stopped channels with MSI IRQ
Clear IEOBs as part of CH stop for channels with MSI IRQ type

Change-Id: I7b9af7f385b0876fc2f43314bd3588110911a021
Acked-by: Nadav Levintov <nadav@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-11 22:51:29 -07:00
Michael Adisumarta
91efd29ef8 msm: ipa3: new low latency data pipes support
Includes low latency data pipe definition and
support for waipio.

Change-Id: I0158eb15b38de0dfd2b0052b699c69a7c7f58fa1
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-05-10 17:21:49 -07:00
qctecmdr
aeea2f09f3 Merge "msm: ipa3: Adding chnages to update event RP from DDR" 2021-05-10 08:58:37 -07:00
Ashok Vuyyuru
9ea98412c7 msm: ipa3: Adding chnages to update event RP from DDR
In suspend scenario while checking channel empty scenario
updating the event ring RP pointer from direct register, it
may cause mismatch in reading in polling context. To avoid
discrepancy  reading RP pointer DDR location.

Change-Id: Ie198ea9ace033e31463acd974f10dccdcac45c55
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-06 22:50:16 +05:30
qctecmdr
5e63fdb447 Merge "msm: ipa: Enable GSI Channel almost empty Feature" 2021-05-05 15:11:15 -07:00
qctecmdr
e7414c97c6 Merge "msm: ipa: add unit tests for NTN3 offload" 2021-05-04 19:03:59 -07:00
Bojun Pan
5ad90dcb6e msm: ipa: Enable GSI Channel almost empty Feature
Enable GSI Channel almost empty Feature for MHI DL channel.

Change-Id: I9e27044f30bf61b91c0dcd7b7f109404b303bb62
2021-04-29 18:33:35 -07:00
Sivan Reinstein
d1dfec34da msm: gsi: add gsi profiling stats and fw version to debugfs
Add GSI profiling stats data and the GSI FW version to debug fs.

Change-Id: I5749339f5ec9656e636a512668025bb09a97a3ec
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-04-29 09:39:20 +03:00
Amir Levy
4d4a72f1da msm: ipa: Add NTN3 debug stats support
Add debugfs support for NTN3 stats.
Collect stats from uC add print from debugfs.

Change-Id: Iaf31beedb7403ee924a170f3b6c45ce0b78b7680
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-11 10:44:56 +03:00
Amir Levy
9115a93389 msm: ipa: add NTN3 offload support
Add NTN3 gsi scratch and protocol.
Add NTN3 support in ipa_eth.

Change-Id: I7dde0f21711617770ea31e325db803108d929565
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-11 10:44:56 +03:00
Chaitanya Pratapa
407bf99e8f msm: ipa: Fix TX NAPI handling
Make changes to ensure NAPI is scheduled only once.
Make changes to use right register
GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k for clearing interrupt.

Change-Id: I8de97f584ac4915d59b6716e7dff0c181a48cd1e
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-04-09 15:40:50 -07:00
Ashok Vuyyuru
9aeec4c5b7 msm: ipa3: Check channel in right state before access base address
Observing use after free issue during teardown WAN pipe if we
receive the incoming packet. Adding check channel in right state
before access base address.

Change-Id: I29a611693b78637811fe45abea93d9ed3e6f54e5
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-03-15 09:32:02 -07:00
Bojun Pan
05f6b458cf msm: ipa: fix the polling state on GSI
Adding the missing change to update the polling state.

Change-Id: Icfd26c17b91cfe62b67a44c27727fff1f14b6943
2021-03-11 09:41:28 -08:00
qctecmdr
7038889f3f Merge "msm: ipa3: Changes to decrease the num_of_chan_allocated count" 2021-03-10 08:44:43 -08:00
Praveen Kurapati
4ab3b7d997 msm: ipa3: Changes to decrease the num_of_chan_allocated count
Observing gsi assert in SSR scenario due to not decreasing the
num_of_chan_allocated count. Adding changes to decrease the count
in dealloc event ring.

Change-Id: Icc0713c25bc5566c377e46fef2a4feb3feed176a
Signed-off-by: Praveen Kurapati <pkurapat@codeaurora.org>
2021-03-10 11:43:41 +05:30
Sivan Reinstein
468a3b7e65 msm: ipa: napi on tx completion changed to polling
Masked interrupts, moved the producer apps
event ring and channel ring polling from
GSI IRQ to napi context, and disabled NOP
descriptors, since interrupt mitigation
is now coming from napi usage.

Change-Id: Id69ba519103255567654d5a11fcd3387900cb27d
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Acked-by: Tal Gelbard <tgelbard@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-03-05 10:26:35 +02:00
Bojun Pan
ac12b70a3c msm: ipa: update gsi config for RTK
1. Change the RTK doorbell to MSI doorbell.
2. Update RTK element size to 32B.

Change-Id: Iec9301e30b51841c139b97abeaa6354a88fdef59
2021-02-11 15:08:17 -08:00
Ashok Vuyyuru
7aa1dc1510 msm: ipa4: Enhanced flow control changes
Adding changes to support enhanced flow control.

Change-Id: Id656319703a27f5073c6fd129fb4202a37b49aad
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-02-09 17:13:28 +05:30
qctecmdr
5015c14a5a Merge "msm: gsi: Fix gsi stop channel fail for old target." 2021-01-27 18:29:11 -08:00
Piyush Dhyani
953369c4de msm: gsi: Fix gsi stop channel fail for old target.
In older target we may not receive gsi interrupt while
stopping the channel in first retry, so we inject dma
1B packet while retrying. We were observing crash during
stop channel as we were reading channel current state
only after interrupt recieved. Now reading channel
current state in case we not recieved interrupt for
older target.

Change-Id: I4f436bee610ce6ccd5e0f4c982689c15291a2011
Signed-off-by: Piyush Dhyani <pdhyani@codeaurora.org>
2021-01-15 19:57:28 +05:30
Chaitanya Pratapa
dddff2741e msm: gsi: remove usage of devm_ioremap_nocache
devm_ioremap_nocache is deprectaed in newer kernels. Make
changes to remove the usage.

Change-Id: I84ad1a8fb707b516a6976d3038878b55ba0dd6b4
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-01-12 17:26:24 -08:00
Chaitanya Pratapa
d10d7d54b9 msm: ipa: align to latest kernel version
Make changes to align to the latest kernel version.
Fixes to compilation errors and forbidden warnings.

Change-Id: I5c7a7b8a8ce2ccd98af3d6458bd6a9bdddeb361b
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-01-06 11:36:48 -08:00
Amir Levy
930033d715 msm: ipa: fix aqc msi address
fix aqc msi address type to build succesfully for
msm and mdm. add gsi offset to returned address.

Change-Id: I36ed6f20daeff90837d5b022c0b51a0c3ea07dec
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2020-12-13 16:26:18 +02:00
qctecmdr
d5689c1472 Merge "msm: ipa3: Fix race condition during teardwon pipe" 2020-12-08 09:31:05 -08:00
qctecmdr
13797b24fb Merge "msm: ipa3: Fix to remove max poll count in gsi isr handle" 2020-12-08 08:00:06 -08:00
Ashok Vuyyuru
b708bca845 msm: ipa3: Fix race condition during teardwon pipe
When endpoint in polling mode possible to pipe teardown trigger parallel
it leads to race condition. Adding changes to check in endpoint came out
of polling mode and continue to teardown the endpoint.

Change-Id: I0b22d6a7a1f5229acec2dbc9dd5cb76488c09faa
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2020-12-08 03:07:37 -08:00
Ashok Vuyyuru
2c38874a5d msm: ipa3: Fix to remove max poll count in gsi isr handle
In SSR scenario possiable to receive the contineous interrupt
when IPA HW recovered from temporary stall. Add changes to
remove the max poll count in gsi isr handle function.

Change-Id: Idaf1d9a070426188f3614ebf85010d0107d79dfb
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2020-12-08 02:58:53 -08:00
qctecmdr
a72e6ebde0 Merge "msm: ipa: Support hardware accelerated DIAG over qdss" 2020-12-08 02:55:59 -08:00
Michael Adisumarta
ae988186cc msm: ipa: Support hardware accelerated DIAG over qdss
Add changes to accelerate QDSS diag traffic over IPA
to the PCIe host.

Change-Id: Ice72f8761d092677d4c5434d87bbed295ac435d6
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2020-12-07 16:16:22 +05:30
Chaitanya Pratapa
6f19cedb0c msm: gsi: dump channel information
Dump channel information when stop channel fails.

Change-Id: I39ef3338c9e7e968ee6a592debc23edbff9f8fc8
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2020-11-24 15:14:39 -08:00
Amir Levy
40fcad23c6 msm: ipa: add AQC support in ipa_eth client
Add AQC support in ipa_eth client framework.

Change-Id: I1eb17ebf02813d59977c8c792923e70f348c9ea9
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
2020-11-15 22:52:32 -08:00
Amir Levy
ace2384057 msm: ipa: create ipa_client for ethernet
Create the ipa_client interface for ethernet offloading.

Change-Id: I8120b0cca9e42a75153fb1468dc1b8bcbd43484c
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2020-11-15 19:30:00 -08:00
qctecmdr
a88b4a4d0c Merge "ipa: MHI: Fix CH Scratch & MHI testing" 2020-11-05 04:31:44 -08:00
Sivan Reinstein
29f6c65440 ipa: MHI: Fix CH Scratch & MHI testing
Fix MHI channel scratch struct and fix MHI testing

Change-Id: I764b11435af3d0cff2fead8a750d22136c7f1ee7
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2020-11-03 08:03:17 +02:00
Sivan Reinstein
c91a30c1de gsi: HAL fix WDI3 MSI address set
Fix GSI HAL setting of MSI address for WDI3 channels

Change-Id: Ic04e435d75a9e7810c87dcab73c2277328ab86d1
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2020-10-19 20:25:54 +03:00
Ilia Lin
98d4a895e0 gsi: Init props in the context before IRQ enable
Once the interrupt is enabled we could get an interrupt
immediately. To avoid a crash in this case, we have
to initialize the props structure in the gsi_ctx.

Change-Id: Ic595bc9d8ab5f3803ff6e1592358f426dcf51e0a
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2020-10-08 09:22:02 +03:00
Sivan Reinstein
2143cb5dd1 gsi: Add HAL Layer for GSI 3.0 version
Update GSI HAL to support GSI 3.0

Change-Id: I7b3a687ddbf51f71011267d6bb9b559eb4a8fbd1
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2020-10-08 09:21:40 +03:00
Sivan Reinstein
b4f2036141 gsi: Add HAL Layer for GSI
Add Hardware Abstraction Layer infrastructure to GSI
driver. This change includes registers HAL component
for GSI.

Change-Id: I87e7c22ed88117a74af4220b4c05c610bae498cc
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2020-10-08 09:20:40 +03:00
Bojun Pan
72e7088c19 msm: ipa4: fix the unclock gsi IPA register access
The while loop in gsi_handle_irq will cause an extra register
read after handle last interrupt. This read can be the unclocked
read. The fix is to break on ch/evt control interrupt where
could potientially cause IPA clock off.

Change-Id: If4b3bb127ee66648d24b8ca7c16bd6fec42d9fcc
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
2020-08-18 23:43:53 -07:00
qctecmdr
10afe9873b Merge "msm: gsi: cache last 20 gsi interrupt for interrupt storm debug" 2020-08-18 14:06:17 -07:00
Ilia Lin
9d4ff10cc6 ipa: Cleanup after moving internal definitions
Removing the files copied from the kernel:
ipa.h
msm_gsi.h
ipa_fmwk.h
ipa_mhi.h
ipa_odu_bridge.h
ipa_uc_offload.h
ipa_usb.h
ipa_wdi3.h
ipa_wigig.h

and including the original files instead.

Depends-on: 3177533

Change-Id: I485f5545505bfbc4e775a75ae3d0809f9a977a97
Signed-off-by: Ilia Lin <ilial@codeaurora.org>
2020-08-12 10:37:35 +03:00
Armaan Siddiqui
9e91a1ef19 msm: ipa: Endpoint configuration and IPA driver changes for mannar
Added Endpoint configuration and IPA driver changes for mannar.

Change-Id: I7424faa1757e7cf81eb9387b63a153cd6b6e607b
2020-08-03 11:28:32 +05:30
Ilia Lin
f8bfa48848 gsi: Init rp_update_vaddr at event ring init
Leaving this field 0 may lead to a crash during
the first gsi_poll_n_channel() call.

Change-Id: I6c8e9e1e5bacdddd41023618881d761d730a1931
Signed-off-by: Ilia Lin <ilial@codeaurora.org>
2020-07-26 22:59:21 +03:00