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msm: ipa: Endpoint configuration and IPA driver changes for mannar

Added Endpoint configuration and IPA driver changes for mannar.

Change-Id: I7424faa1757e7cf81eb9387b63a153cd6b6e607b
Armaan Siddiqui 5 gadi atpakaļ
vecāks
revīzija
9e91a1ef19

+ 21 - 0
drivers/platform/msm/gsi/gsi.c

@@ -909,6 +909,13 @@ static uint32_t gsi_get_max_channels(enum gsi_ver ver)
 			GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
 			GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
 		break;
+	case GSI_VER_2_11:
+		reg = gsi_readl(gsi_ctx->base +
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
+		reg = (reg &
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
+		break;
 	default:
 		GSIERR("GSI version is not supported %d\n", ver);
 		break;
@@ -983,6 +990,13 @@ static uint32_t gsi_get_max_event_rings(enum gsi_ver ver)
 			GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
 			GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
 		break;
+	case GSI_VER_2_11:
+		reg = gsi_readl(gsi_ctx->base +
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
+		reg = (reg &
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
+			GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
+		break;
 	default:
 		GSIERR("GSI version is not supported %d\n", ver);
 		break;
@@ -1112,6 +1126,7 @@ int gsi_register_device(struct gsi_per_props *props, unsigned long *dev_hdl)
 	case GSI_VER_2_5:
 	case GSI_VER_2_7:
 	case GSI_VER_2_9:
+	case GSI_VER_2_11:
 		needed_reg_ver = GSI_REGISTER_VER_2;
 		break;
 	case GSI_VER_ERR:
@@ -4136,6 +4151,9 @@ static void gsi_configure_ieps(void *base, enum gsi_ver ver)
 	if (ver >= GSI_VER_2_5)
 		gsi_writel(17,
 			gsi_base + GSI_V2_5_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS);
+	if (ver >= GSI_VER_2_11)
+		gsi_writel(18, gsi_base + GSI_GSI_IRAM_PTR_MSI_DB_OFFS);
+
 }
 
 static void gsi_configure_bck_prs_matrix(void *base)
@@ -4293,6 +4311,9 @@ void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset,
 	case GSI_VER_2_9:
 		maxn = GSI_V2_9_GSI_INST_RAM_n_MAXn;
 		break;
+	case GSI_VER_2_11:
+		maxn = GSI_V2_11_GSI_INST_RAM_n_MAXn;
+		break;
 	case GSI_VER_ERR:
 	case GSI_VER_MAX:
 	default:

+ 1 - 0
drivers/platform/msm/gsi/gsi.h

@@ -85,6 +85,7 @@ enum gsi_ver {
 	GSI_VER_2_5 = 6,
 	GSI_VER_2_7 = 7,
 	GSI_VER_2_9 = 8,
+	GSI_VER_2_11 = 9,
 	GSI_VER_MAX,
 };
 

+ 41 - 1
drivers/platform/msm/gsi/gsi_reg_v2.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __GSI_REG_V2_H__
@@ -443,6 +443,8 @@
 #define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191
 #define GSI_V2_7_GSI_INST_RAM_n_MAXn 5119
 #define GSI_V2_9_GSI_INST_RAM_n_MAXn 6143
+#define GSI_V2_11_GSI_INST_RAM_n_MAXn 5119
+
 
 #define GSI_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000
 #define GSI_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18
@@ -942,6 +944,44 @@
 #define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
 #define GSI_V2_9_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
 
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_OFFS(n) \
+				(GSI_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n))
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_MAXn 2
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
+#define GSI_V2_11_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5
+#define GSI_GSI_IRAM_PTR_MSI_DB_OFFS \
+		(GSI_GSI_REG_BASE_OFFS + 0x00000414)
+#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_RMSK 0xfff
+#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_IRAM_PTR_BMSK 0xfff
+#define GSI_GSI_IRAM_PTR_MSI_DB_FULL_IRAM_PTR_SHFT 0x0
+
 #define GSI_EE_n_GSI_SW_VERSION_OFFS(n) \
 	(GSI_GSI_REG_BASE_OFFS + 0x00012044 + 0x4000 * (n))
 #define GSI_EE_n_GSI_SW_VERSION_MAJOR_BMSK 0xf0000000

+ 3 - 0
drivers/platform/msm/ipa/ipa_v3/ipa.c

@@ -5973,6 +5973,9 @@ static enum gsi_ver ipa3_get_gsi_ver(enum ipa_hw_type ipa_hw_type)
 	case IPA_HW_v4_9:
 		gsi_ver = GSI_VER_2_9;
 		break;
+	case IPA_HW_v4_11:
+		gsi_ver = GSI_VER_2_11;
+		break;
 	default:
 		IPAERR("No GSI version for ipa type %d\n", ipa_hw_type);
 		WARN_ON(1);

+ 373 - 1
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

@@ -187,6 +187,10 @@
 #define IPA_v4_9_SRC_GROUP_MAX		(3)
 #define IPA_v4_9_DST_GROUP_MAX		(4)
 
+#define IPA_v4_11_GROUP_UL_DL		(0)
+#define IPA_v4_11_SRC_GROUP_MAX		(1)
+#define IPA_v4_11_DST_GROUP_MAX		(1)
+
 #define IPA_GROUP_MAX IPA_v3_0_GROUP_MAX
 
 enum ipa_rsrc_grp_type_src {
@@ -263,6 +267,7 @@ enum ipa_ver {
 	IPA_4_5_APQ,
 	IPA_4_7,
 	IPA_4_9,
+	IPA_4_11,
 	IPA_VER_MAX,
 };
 
@@ -444,6 +449,19 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config
 		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
 		{30, 30}, {8, 8}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
 	},
+	[IPA_4_11] = {
+		/* UL_DL   other are invalid */
+		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
+		{6, 6}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = {
+		{8, 8}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
+		{18, 18}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
+		{2, 2}, {0, 0}, {0, 0},  {0, 0}, {0, 0}, {0, 0} },
+		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
+		{15, 15}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+	},
 
 };
 
@@ -542,6 +560,13 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
 		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
 		{2, 3}, {1, 2}, {0, 2}, {0, 0}, {0, 0}, {0, 0} },
 	},
+	[IPA_4_11] = {
+		/* UL/DL/DPL, other are invalid */
+		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
+		{3,3}, {0, 0}, {25, 25}, {0, 0}, {0, 0}, {0, 0} },
+		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
+		{2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+	},
 
 };
 
@@ -612,7 +637,11 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
 		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
 		{3, 3}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
 	},
-
+	[IPA_4_11] = {
+		/* unused  UL_DL  unused unused  UC_RX_Q  N/A */
+		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
+		{3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+	},
 };
 
 static const u32 ipa3_rsrc_rx_grp_hps_weight_config
@@ -690,6 +719,7 @@ static const struct ipa_qmb_outstanding ipa3_qmb_outstanding
 	[IPA_4_5_APQ][IPA_QMB_INSTANCE_PCIE]	= {12, 8, 0},
 	[IPA_4_7][IPA_QMB_INSTANCE_DDR]	        = {13, 12, 120},
 	[IPA_4_9][IPA_QMB_INSTANCE_DDR]	        = {16, 8, 120},
+	[IPA_4_11][IPA_QMB_INSTANCE_DDR]	= {13, 12, 120},
 };
 
 struct ipa_ep_configuration {
@@ -3079,6 +3109,209 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
 			QMB_MASTER_SELECT_DDR,
 			{ 16, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
 
+	/* IPA_4_11 */
+	[IPA_4_11][IPA_CLIENT_WLAN1_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 3, 3, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
+	[IPA_4_11][IPA_CLIENT_USB_PROD] 		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_APPS_LAN_PROD]	  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 4, 4, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
+	[IPA_4_11][IPA_CLIENT_APPS_WAN_PROD]	  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 2, 2, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } },
+	[IPA_4_11][IPA_CLIENT_APPS_CMD_PROD]	  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+			QMB_MASTER_SELECT_DDR,
+			{ 7, 5, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 8 } },
+	[IPA_4_11][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD]	  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+			QMB_MASTER_SELECT_DDR,
+			{ 1, 1, 4, 4, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 } },
+	[IPA_4_11][IPA_CLIENT_Q6_WAN_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
+	[IPA_4_11][IPA_CLIENT_Q6_CMD_PROD]			= {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 8 } },
+	[IPA_4_11][IPA_CLIENT_Q6_DL_NLO_DATA_PROD]  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 8, 2, 24, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } },
+	/* Only for test purpose */
+	[IPA_4_11][IPA_CLIENT_TEST_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 0, 0, 8, 16, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST1_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 0, 0, 8, 16, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST2_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 1, 1, 8, 16, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST3_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 2, 2, 16, 32, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST4_PROD]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			true,
+			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+			QMB_MASTER_SELECT_DDR,
+			{ 1, 1, 8, 16, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_WLAN1_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 18, 9, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
+	[IPA_4_11][IPA_CLIENT_USB_CONS] 		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 19, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_USB_DPL_CONS] 	   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 17, 8, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_ODL_DPL_CONS] 	   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 22, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_APPS_LAN_CONS]	   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 9, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_APPS_WAN_CONS]	   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 16, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_APPS_WAN_COAL_CONS]		= {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 15, 6, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
+        [IPA_4_11][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] =           {
+                        true, IPA_v4_11_GROUP_UL_DL,
+                        false,
+                        IPA_DPS_HPS_SEQ_TYPE_INVALID,
+                        QMB_MASTER_SELECT_DDR,
+                        { 20, 11, 4, 4, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 } },
+	[IPA_4_11][IPA_CLIENT_Q6_LAN_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 10, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_Q6_WAN_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 14, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
+	[IPA_4_11][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 12, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
+	[IPA_4_11][IPA_CLIENT_Q6_UL_NLO_ACK_CONS]  = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 13, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },
+	[IPA_4_11][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 11, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },
+/* Only for test purpose */
+	/* MBIM aggregation test pipes should have the same QMB as USB_CONS */
+	[IPA_4_11][IPA_CLIENT_TEST_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 16, 7, 9, 9, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST1_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 16, 7, 9, 9, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST2_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 21, 12, 9, 9, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST3_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 19, 10, 9, 9, IPA_EE_AP } },
+	[IPA_4_11][IPA_CLIENT_TEST4_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 20, 11, 9, 9, IPA_EE_AP } },
+	/* Dummy consumer (pipe 31) is used in L2TP rt rule */
+	[IPA_4_11][IPA_CLIENT_DUMMY_CONS]		   = {
+			true, IPA_v4_11_GROUP_UL_DL,
+			false,
+			IPA_DPS_HPS_SEQ_TYPE_INVALID,
+			QMB_MASTER_SELECT_DDR,
+			{ 31, 31, 8, 8, IPA_EE_AP } },
 
 };
 
@@ -3549,6 +3782,100 @@ static struct ipa3_mem_partition ipa_4_9_mem_part = {
 	.end_ofst		= 0x4850,
 };
 
+static struct ipa3_mem_partition ipa_4_11_mem_part = {
+        .uc_info_ofst                   = 0x80,
+        .uc_info_size                   = 0x200,
+        .ofst_start                     = 0x280,
+        .v4_flt_hash_ofst               = 0x288,
+        .v4_flt_hash_size               =  0x78,
+        .v4_flt_hash_size_ddr           = 0x4000,
+        .v4_flt_nhash_ofst              = 0x308,
+        .v4_flt_nhash_size              = 0x78,
+        .v4_flt_nhash_size_ddr          = 0x4000,
+        .v6_flt_hash_ofst               = 0x388,
+        .v6_flt_hash_size               = 0x78,
+        .v6_flt_hash_size_ddr           = 0x4000,
+        .v6_flt_nhash_ofst              = 0x408,
+        .v6_flt_nhash_size              = 0x78,
+        .v6_flt_nhash_size_ddr          = 0x4000,
+        .v4_rt_num_index                = 0xf,
+        .v4_modem_rt_index_lo           = 0x0,
+        .v4_modem_rt_index_hi           = 0x7,
+        .v4_apps_rt_index_lo            = 0x8,
+        .v4_apps_rt_index_hi            = 0xe,
+        .v4_rt_hash_ofst                = 0x488,
+        .v4_rt_hash_size                = 0x78,
+        .v4_rt_hash_size_ddr            = 0x4000,
+        .v4_rt_nhash_ofst               = 0x508,
+        .v4_rt_nhash_size               = 0x78,
+        .v4_rt_nhash_size_ddr           = 0x4000,
+        .v6_rt_num_index                = 0xf,
+        .v6_modem_rt_index_lo           = 0x0,
+        .v6_modem_rt_index_hi           = 0x7,
+        .v6_apps_rt_index_lo            = 0x8,
+        .v6_apps_rt_index_hi            = 0xe,
+        .v6_rt_hash_ofst                = 0x588,
+        .v6_rt_hash_size                = 0x78,
+        .v6_rt_hash_size_ddr            = 0x4000,
+        .v6_rt_nhash_ofst               = 0x608,
+        .v6_rt_nhash_size               = 0x78,
+        .v6_rt_nhash_size_ddr           = 0x4000,
+        .modem_hdr_ofst                 = 0x688,
+        .modem_hdr_size                 = 0x240,
+        .apps_hdr_ofst                  = 0x8c8,
+        .apps_hdr_size                  = 0x200,
+        .apps_hdr_size_ddr              = 0x800,
+        .modem_hdr_proc_ctx_ofst        = 0xad0,
+        .modem_hdr_proc_ctx_size        = 0x200,
+        .apps_hdr_proc_ctx_ofst         = 0xcd0,
+        .apps_hdr_proc_ctx_size         = 0x200,
+        .apps_hdr_proc_ctx_size_ddr     = 0x0,
+        .nat_tbl_ofst                   = 0xee0,
+        .nat_tbl_size                   = 0xd00,
+        .pdn_config_ofst                = 0x1be8,
+        .pdn_config_size                = 0x50,
+        .stats_quota_q6_ofst            = 0x1c40,
+        .stats_quota_q6_size            = 0x30,
+        .stats_quota_ap_ofst            = 0x1c70,
+        .stats_quota_ap_size            = 0x48,
+        .stats_tethering_ofst           = 0x1cb8,
+        .stats_tethering_size           = 0x238,
+        .stats_flt_v4_ofst              = 0,
+        .stats_flt_v4_size              = 0,
+        .stats_flt_v6_ofst              = 0,
+        .stats_flt_v6_size              = 0,
+        .stats_rt_v4_ofst               = 0,
+        .stats_rt_v4_size               = 0,
+        .stats_rt_v6_ofst               = 0,
+        .stats_rt_v6_size               = 0,
+        .stats_fnr_ofst                 = 0x1ef0,
+        .stats_fnr_size                 = 0x0,
+        .stats_drop_ofst                = 0x1ef0,
+        .stats_drop_size                = 0x20,
+        .modem_comp_decomp_ofst         = 0x0,
+        .modem_comp_decomp_size         = 0x0,
+        .modem_ofst                     = 0x1f18,
+        .modem_size                     = 0x100c,
+        .apps_v4_flt_hash_ofst  = 0x1f18,
+        .apps_v4_flt_hash_size  = 0x0,
+        .apps_v4_flt_nhash_ofst = 0x1f18,
+        .apps_v4_flt_nhash_size = 0x0,
+        .apps_v6_flt_hash_ofst  = 0x1f18,
+        .apps_v6_flt_hash_size  = 0x0,
+        .apps_v6_flt_nhash_ofst = 0x1f18,
+        .apps_v6_flt_nhash_size = 0x0,
+        .apps_v4_rt_hash_ofst   = 0x1f18,
+        .apps_v4_rt_hash_size   = 0x0,
+        .apps_v4_rt_nhash_ofst  = 0x1f18,
+        .apps_v4_rt_nhash_size  = 0x0,
+        .apps_v6_rt_hash_ofst   = 0x1f18,
+        .apps_v6_rt_hash_size   = 0x0,
+        .apps_v6_rt_nhash_ofst  = 0x1f18,
+        .apps_v6_rt_nhash_size  = 0x0,
+        .uc_descriptor_ram_ofst = 0x3000,
+        .uc_descriptor_ram_size = 0x0000,
+        .end_ofst               = 0x3000,
+};
 
 
 const char *ipa_clients_strings[IPA_CLIENT_MAX] = {
@@ -3720,6 +4047,9 @@ const char *ipa_get_version_string(enum ipa_hw_type ver)
 	case IPA_HW_v4_9:
 		str = "4.9";
 		break;
+	case IPA_HW_v4_11:
+		str = "4.11";
+		break;
 	default:
 		str = "Invalid version";
 		break;
@@ -4143,6 +4473,9 @@ u8 ipa3_get_hw_type_index(void)
 	case IPA_HW_v4_9:
 		hw_type_index = IPA_4_9;
 		break;
+	case IPA_HW_v4_11:
+		hw_type_index = IPA_4_11;
+		break;
 	default:
 		IPAERR("Incorrect IPA version %d\n", ipa3_ctx->ipa_hw_type);
 		hw_type_index = IPA_3_0;
@@ -6130,6 +6463,9 @@ int ipa3_init_mem_partition(enum ipa_hw_type type)
 	case IPA_HW_v4_9:
 		ipa3_ctx->ctrl->mem_partition = &ipa_4_9_mem_part;
 		break;
+	case IPA_HW_v4_11:
+		ipa3_ctx->ctrl->mem_partition = &ipa_4_11_mem_part;
+		break;
 	case IPA_HW_None:
 	case IPA_HW_v1_0:
 	case IPA_HW_v1_1:
@@ -7712,6 +8048,36 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index,
 			}
 		}
 		break;
+	case IPA_4_11:
+			if (src) {
+				switch (group_index) {
+				case IPA_v4_11_GROUP_UL_DL:
+					ipahal_write_reg_n_fields(
+						IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,
+						n, val);
+					break;
+				default:
+					IPAERR(
+					" Invalid source resource group,index #%d\n",
+					group_index);
+					break;
+				}
+			} else {
+				switch (group_index) {
+				case IPA_v4_11_GROUP_UL_DL:
+					ipahal_write_reg_n_fields(
+						IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
+						n, val);
+					break;
+				default:
+					IPAERR(
+					" Invalid destination resource group,index #%d\n",
+					group_index);
+					break;
+				}
+			}
+			break;
+
 
 	default:
 		IPAERR("invalid hw type\n");
@@ -7877,6 +8243,12 @@ void ipa3_set_resorce_groups_min_max_limits(void)
 		src_grp_idx_max = IPA_v4_9_SRC_GROUP_MAX;
 		dst_grp_idx_max = IPA_v4_9_DST_GROUP_MAX;
 		break;
+	case IPA_4_11:
+		src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;
+		dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;
+		src_grp_idx_max = IPA_v4_11_SRC_GROUP_MAX;
+		dst_grp_idx_max = IPA_v4_11_DST_GROUP_MAX;
+		break;
 	default:
 		IPAERR("invalid hw type index\n");
 		WARN_ON(1);