The hs timer control settings can't match with dsi data transfer
requirement, so it may lead to timeout issue when running into low
frame rate, update this change to fix such issue for 30hz display
mode.
Change-Id: I01942a494f46e0023061a9d307a9d2ca1fd8159a
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Add existing debug logs to ipc logging to be
accessed through debugfs.
Change-Id: Id9bfe61cb7921674eadc5635847c81a0fbdaef5c
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
When destination scaler feature is enabled along with demura,
the crtc w/h will be lesser than the deumra layer w/h as it is
based on the panel w/h. Remove the invalid validation of
demura layers against crtc w/h to allow this usecase.
Change-Id: I5afd0407382a1bce458c97fcf8d571f5e7c0774f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
If LFC of demura is disabled, there are few parameters that needs to be
set in demura hardware block. Change ensures that the mandatory params
are set.
Change-Id: Ia2b7d80ccc60c19b7106ed417e7803a205bef6ff
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
pll_codes_region is not defined on TVM and not programmed.
So, adding TVM check to avoid parsing pll code data.
Change-Id: Ia6280ca3fc1b19866673a6767de465d17681add7
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add bound check for number of dnsc_blur blocks, while parsing from
device tree. Fix out of bound access while setting the llcc_active
during system cache disable case in writeback.
Change-Id: I7e604db5ebfaa6e8b6f066e0f6efb76e7d78e604
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change provides required support to disable display module
compilation along with all modules and supports module specific
override to enable compilation if required.
Change-Id: I38acdce4083e38245eb6285c99d5dbbd15911fbb
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Currently, _msm_seamless_for_crtc returns true when multiple connectors
are attached to the old_crtc_state and connector_changed flag is set.
The crtc disable is skipped due to this check when the suspend request
comes with primary + cwb. This makes the sde crtc out of sync between
user-mode and driver. Fix this by avoiding crtc seamless check when
active_changed is set as in those cases, crtc enable/disable has to
executed.
Change-Id: Ibe4e3996009712d3bd6a13651b051d5e89ec131a
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When qsync is enabled with a large threshold start window, there
is a chance that two frames can be latched by mdp HW in single
vsync window. This change overrides the tearcheck rd_ptr_val
to a value larger than the end of the Tear check start window
to ensure new frame is not latched in current vsync window.
Change-Id: I21273f0bca83747210792b911e964dfd2d50079f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change moves warning log to info log if secondary default panel
is not available.
Change-Id: Iad420a05c6440afdf0fcc5f7d33197eaf5c158c4
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
When display is left on from the bootloader, disp_cc driver will put a
proxy vote on clocks to maintain the hardware configuration of bootloader.
Once all the consumers have been probed, the dispcc driver will synchronize
the hardware state of the device to match the aggregated software state
requested by all the consumers using sync_state call.
If there is an idle power collapse or a suspend before sync state call,
branch clocks and in turn RCG will not get turned off during clocks
disable sequence because of the proxy vote of disp_cc driver. This can be
the case even if there is a vote from any other disp_cc consumers.
During a subsequent call to enable the clocks from DSI driver, we are
currently switching RCG parent to PLL and then turning on the PLL.
If the sync state call doesn't happen before we enable the clocks back,
we'll be setting PLL which is off as a parent to RCG that is on.
But ideally when RCG is on, both the old and new sources should be on
while switching the RCG parent.
Avoid this by turning on the PLL before switching RCG parent during clock
enable sequence.
Change-Id: I1597cf2c8095957cd2b2a20a72bf7199e0d61809
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Acquire dsi_ctrl->ctrl_lock lock before programming dsi ctrl
registers. Failing this may lead to race conditions in register
programming.
Add missing mutex lock inside dsi_ctrl_host_timing_update().
Change-Id: Ic86cbe282333c0b4d63ae3d5b3356a5d24752203
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Add crtc checks to ensure the crtc width is always even number,
so there is no loss while dividing by num_mixers. Add checks in
dnsc_blur to ensure the src is always greater than the dest.
Change-Id: I876f19aa20857dc9ed2649c9cb7569348e7d5fd3
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support for localized CLK_CTRL access through LUTDMA
hardware block.
This change aggregates RD/WR LUTDMA CLK_CTRL in a single
ops.
Change-Id: Id5c24bebf7dfcd9f768b2a6f6fa03f8b01747354
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering
this suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.
Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Some of the display status changes such as re-enable
or re-disable are not critical errors and can be ignored.
This change downgrades such errors as warnings.
Change-Id: I6800e534fc7fb825a472f37bb78a928e2e78d63a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently in an MST scenario, DSC resources are updated in
bookkeeping only when the corresponding stream is enabled.
This would lead to assigning already reserved DSC blocks to the
2nd stream, if 2nd stream is validated before the 1st stream is
enabled. This change would update the bookkeeping as soon as the
mode is validated.
Change-Id: I7f89a16639efcde3e5dfdf423715ed354e1de66a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change disables hw_fences when a mode switch
from video to command mode or command to video mode
is ongoing.
Change-Id: I6f99226b59b381c6d2ff34a85753f8608080f546
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
remove the TARGET_BOARD_AUTO flag check to enable
the display driver msm_drm.ko packing for automotive builds.
Change-Id: I3eda4b3ecb497be71cbe156acb62a0731f12ccde
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Change removes downstream parsing of deep color modes function
_sde_edid_update_dc_modes, which is presently parsed in upstream
function drm_parse_ycbcr420_deep_color_info in drm_edid file.
Change-Id: I4426e190cdc1e5f139a0c0439cc45f3cc7884c3d
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
