Since the CCI error isn't fatal error during probing sensor,
so we can just print an info log for the CCI error.
CRs-Fixed: 3118450
Change-Id: Ie980c9eb37e410b07c434a7a304ab1c18925319b
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
When KMD faces overflow errors, it will try internal recovery
first, every time KMD do internal recovery, it notifies to UMD
to do according process.
CRs-Fixed: 3131351
Change-Id: I06e7dc3c258b12fc2865d3383280a456b42c2163
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
This fix addresses the current problem of ICP communicating through HFI
prior to HFI being set up.
CRs-Fixed: 3130279
Change-Id: I306b6dd85eb08b7c5c6f49f9f2aad05a42b394bc
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
On CSID encountering a fatal rx error, notify phy to update it's
aux settings for the given data rate when it streams on the
next time. The phy device will book keep all the data
rates that need updated aux settings and on all the
occasions they are streamed on the updated aux settings will
be configured. This is supported for all data rates
from 1.2 - 2.35 GSpS. The change also adds a debugfs in phy driver
to disable aux settings update altogether.
CRs-Fixed: 3120043
Change-Id: Ia1ea3b9278c2eb918a527ee3d7b1ecfe53c4f2c2
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Instead of correct link handle, if some other handle like
dev handle is passed then it may access some other data space.
To avoid such scenario, need to check whether link handle
passed by ioctl is same as retrieved link handle.
CRs-Fixed: 3120454
Change-Id: Idff2e3c25b60563788ffb426c7cabc367c3c97f8
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
Add back in check for ddr memory type to distinguish between DDR4/5
memory types.
CRs-fixed: 3136181
Change-Id: Ia152cde2786bf6e3da172d2b7046f9871d4f8e3c
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Signed-off-by: Wasim Khan <quic_wasikhan@quicinc.com>
Fix the CPAS Start and CPAS stop call sequence
for the Sensor power up. Also, only start and stop
the CPAS when we really want to write to the
AON-Main Camera Mux register.
CRs-Fixed: 3134267
Change-Id: If73ddc838d59a71f0e6cd21d390c7e603c42b2d6
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Without this, tpg is keeping refCount on titan top gdsc and
thus causing qchannel handshake side effects.
Sequence:
1. TPG calls cpas_start, increments refCount on gdsc with
soc_enable_resources
2. run usecase
3. TPG missing disable_soc_resource
4. TPG calling cpas_stop : which shuts down qchannel
5. When next iteration starts, because gdsc is still on from
previous session, cpas top is not getting reset state
registers - thus keeping qchannel still in shut down state.
qchannel goes to good state if gdsc is actually turned off
and then turned on.
CRs-Fixed: 3131613
Change-Id: Iacb837f7ee3fd7d6b094d0271d0f2d9c15f0b306
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
For some chipsets, qchannel handshake needs icp clk to be
enabled. Add support to enable icp clk while qchannel
handshake by adding as optional clk in cpas node. Whether
to enable icp clk or not is controlled through workaround
list populated for each chipset.
Add mechanism to retry qchannel acceptance if the first
auto try has failed, by explicity writing 0x1 to qchannel
ctrl register. This will bring back qchannel to good state.
CRs-Fixed: 3131613
Change-Id: Ie39a9789b2eb1bf9c0f6adb26fe6d6e1823eff70
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add CDM core registers dump functionality for
the scenariors where the cdm reset timesout and
the workqueue is delayed.
CRs-Fixed: 3130212
Change-Id: Ib79bb24164c77082eacfbecd14795b726bb14201
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
bufq mutex can be destroyed at unmap, if other thread
is trying to lock the bufq mutex it can result in
bad magic number. To avoid such race condition
check bitmap with protection of global mutex lock.
CRs-Fixed: 3120472
Change-Id: Id95be0faa5b0d921c4a0370ea5d2f3b23c229280
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Add support to report causes of fence errors for ICP and IFE.
The change also reports ICP critical failures like WD bark
and system error to userspace.
CRs-Fixed: 3035452
Change-Id: I699621ae71e0f8902cb7b9d42203effd2e2e40de
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Change flush request active and flush request pending arrays from
static of size 20 to dynamically allocated size based on current
pending and active request lists.
CRs-Fixed: 3046003
Change-Id: Iaa1179881d786359dbe9d37411a6ef3ae8038227
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Currently main/aon control operation is getting trigger explicitly
from probe control with the reason that Probe IOCTL is exclusive to
sensor core. This operation is required for making sure to get the
control to hlos before reading slave id. Further post probe operation
main/aon control selection is managed by csiphy driver at the time of
acquire and release ioctl call. This will block the main camera
operation after probe ioctl successful and before csiphy acquire ioctl
call. There are some usecase where sensor needs to perform several
operation independently. To add this support moving the main/aon
selection call from probe only ioctl operation to power_up/down call
flow. This call is made upon when it is required to operate on sensor.
This change will help to give AON sensor more flexibility to perform
independently. Further CSIPHY also have the same selection process
in it's acquire ioctl operation which can help to make the hlos end
selection in combo mode scenario.
CRs-Fixed: 3084672
Change-Id: Ic1c6ad41e35605a2291e7e50ff0fe94a0ab30624
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
camera-kernel:
7d373a7 Merge "msm: camera: csiphy: Update the csiphy bring up sequence" into camera-kernel.lnx.dev
e415498 Merge "msm: camera: icp: Dump ICP fault/CSR registers on HFI init failure" into camera-kernel.lnx.dev
f6a93b2 Merge "msm: camera: smmu: add new flag to indicate Hw, CDM access" into camera-kernel.lnx.dev
971dc5d Merge "msm: camera: common: Update logging for better debugging" into camera-kernel.lnx.dev
a4adec8 Merge "msm: camera: sfe: Fix truncation of 64bit address" into camera-kernel.lnx.dev
11cb115 Merge "msm: camera: smmu: set 64bit mask to utilize 64GB space for camera CBs" into camera-kernel.lnx.dev
Change-Id: Ibc72134b5e7bfdc9e162553574e5a4a3da372750
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
If HFI init times out, log ICP status and CSR registers.
CRs-Fixed: 3110947
Change-Id: I611c29ee1b48f210f76750e57f38e260278b6812
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
When set, buffers will be mapped within 32-bit region
address space and in patching, if Shared or CmdBUffer is
not set for such buffers - patch the value with right shift
by 8. kmd does as below.
Map:
Shared or CmdBuffer : Mapped within 32bit.
HwAndCDMOrShared : Mapped within 32bit
others(HwAccess) : Mapped within 40bit
Patching:
Shared or CmdBuffer : as is
HwAndCDMOrShared : iova >> 8
others (HwAccess) : iova >> 8
Shared/CmdBuffer takes precedence over HwAndCDMOrShared.
CRs-Fixed: 3128094
Change-Id: Ifd9f5beaf2659f77544cd0722ef7f60d6c0684a7
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Update the csiphy header 2.1.2 with the new bring up
sequence revision 11.
CRs-Fixed: 3127494
Change-Id: I9a3579ecd2fc2274cf9913af0ef054cc62343b0e
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
While saving iova address, we were saving into uint32 which is
truncating the address. When this address is programmed to hw,
its causing page fault. Fix by saving the iova first into
dma_addr_t which is uint64 and then calculate base and offset
register values to program to hw.
CRs-Fixed: 3128094
Change-Id: Ie8dc8cbd9848267b7b50db5ef987bd06518cc357
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
To utilize more than 32-bit address space, clients need to call
dma_set_mask_and_coherent API. When called with particular value,
the max address range thats mapped on this context bank is
min of this mask value and value_from_iommu-dma_addr_pool.
CRs-Fixed: 3128094
Change-Id: Ib48dc0b00f8e915ca7faa367bec7473aed9931b4
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add support to enable SFE/IFE perf counters by allowing
user to configure the counters. By default the counter
values are dumped at EOF.
To configure the counter-
adb shell cat /sys/kernel/debug/camera/ife/isp_perf_counters
adb shell "echo "ife_1_2162693" >
/sys/kernel/debug/camera/ife/isp_perf_counters"
A read on the debugfs file will list the available counters
on the target for the different HW blocks.
The change also adds support to configure CSID test bus.
adb shell "echo <reg_val> >
/sys/kernel/debug/camera/ife/ife_csid_testbus".
CRs-Fixed: 3110947
Change-Id: Idc3952e64c943acd1d1893ed24eea88cf9908100
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Force callers to say if they are using 36 bit address patching or not.
CRs-fixed: 3121782
Change-Id: I4dee25e3f73104a1be043fe18a295cd4f8447821
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Print out WM information on CCIF violation.
CRs-Fixed: 3121755
Change-Id: I0fffd8cf4bc7af660f120ba1df8917cd95af64b4
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Corrects the variable debug print statements for expanded memory case
in IFE.
CRs-Fixed: 3120109
Change-Id: I08e2849db21459ebaecec68a7340d8d103562743
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Due to hw limitation, if the required RDI buffer output is
Plain16_10/12/14, BUS cannot conver CSID unpacked MSB data
into LSB aligned while writing the buffers. So keep CSID out
as unpacked LSB data if the final RDI output buffer format
is Plain16_10/12/14. This will have limitation in using RDI
data going into LCR/PDAF.
CRs-Fixed: 3118104
Change-Id: I9193530ec549b4658a058ae71eed4f31653bd88e
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Currently lane specific general register programming is structured
with lane index basis. This is not required as general register
needs to program without any condition. This change updates structure
of this programming register. Also, array size calculation is replace
with more intutive way rather to manually enter the size everytime.
CRs-Fixed: 3117726
Change-Id: I5e57f37bf2025b37f23c10b835fd31ddfe986cee
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To avoid concurrent access to the device timers while
stopping them, keep the stop call protected with hw
mutex.
CRs-Fixed: 3080397
Change-Id: If0a5226536e3a3c14738811965511225d1a96f08
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Extension of Let's do a reset (LDAR) for ICP to include more info.
CRs-Fixed: 3105929
Change-Id: I5fee181d009a8d69e8d3e673a552b289f72fb4aa
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
camera-kernel:
48c1c34 Merge "msm: camera: csiphy: Add lane enable register capability" into camera-kernel.lnx.dev
f354ed9 Merge "msm: camera: isp: Keep the data in MSB while unpacking at CSID" into camera-kernel.lnx.dev
Change-Id: If82b6a657c246dfc1872ef65acc17e939da4ec32
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
BUS, SFE pipeline(xCFA), PDAF/RDI-LCR pipeline expects the
incoming valid data to be in MSB. So, if RDI data is unpacked
to PLAIN_16 at CSID out, keep the valid data in MSB.
For final out formats PLAIN16_10/12/14/16 formats, unpack
data at CSID and keep in MSB and use wm pack with LSB write,
as LCR/PDAF can be enabled with these final out formats and
expects data in MSB.
CRs-Fixed: 3118104
Change-Id: Idb64d809ea006192eb29bb9bb57c5c12a6e8b136
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add and handle lane enable register offset programming independent
than common control register array.
CRs-Fixed: 3117726
Change-Id: I7a9cfe41cb425143bf2be6c48de47dfb5e117aae
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To configure CP mask correct version check needs to be
used against CPAS hw version. Currently csiphy driver
is checking platform version to make the decision.
This change update this check with CPAS hw version check.
CRs-Fixed: 3048249
Change-Id: Id023f5cc0252b47c274dfed9d93e7f49a3d0ab49
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
After flushed, KMD reports ERR including isp, actuator, sensor, flash.
However many CRs don't have fatal KMD error log, but participant is KMD.
Remove the non-fatal KMD error log.
CRs-Fixed: 3095401
Change-Id: I0e5e370c0c4d1daceb72d9eed8d0c45baad5179e
Signed-off-by: Wang Kan <quic_wkan@quicinc.com>
camera-kernel:
c8e56da Merge "msm: camera: cdm: Fix the CDM Reg dump" into camera-kernel.lnx.dev
e63fee2 Merge "msm: camera: isp: Add support for the new error codes" into camera-kernel.lnx.dev
Change-Id: I5a62e828fbaa686af2b2dd84f1ad879cf6562b5e
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
