msm: camera: common: Add support to update auxiliary settings

On CSID encountering a fatal rx error, notify phy to update it's
aux settings for the given data rate when it streams on the
next time. The phy device will book keep all the data
rates that need updated aux settings and on all the
occasions they are streamed on the updated aux settings will
be configured. This is supported for all data rates
from 1.2 - 2.35 GSpS. The change also adds a debugfs in phy driver
to disable aux settings update altogether.

CRs-Fixed: 3120043
Change-Id: Ia1ea3b9278c2eb918a527ee3d7b1ecfe53c4f2c2
Signed-off-by: Jigar Agrawal <[email protected]>
Signed-off-by: Karthik Anantha Ram <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/iopoll.h>
@@ -44,10 +45,7 @@
 /* Max number of sof irq's triggered in case of SOF freeze */
 #define CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX 12
 
-/* Max CSI Rx irq error count threshold value */
-#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT               100
-
-#define CAM_IFE_CSID_VER1_STATUS_MAX_NUM 32
+#define CAM_IFE_CSID_VER1_STATUS_MAX_NUM               32
 
 static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
 	{
@@ -3352,8 +3350,7 @@ static int cam_ife_csid_ver1_sof_irq_debug(
 			csid_hw->rx_cfg.phy_sel);
 
 	cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-			CAM_SUBDEV_MESSAGE_IRQ_ERR,
-			(void *)&data_idx);
+		CAM_SUBDEV_MESSAGE_REG_DUMP, (void *)&data_idx);
 
 	return 0;
 }
@@ -4092,8 +4089,8 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
 			event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
 
 		cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-				CAM_SUBDEV_MESSAGE_IRQ_ERR,
-				(void *)&data_idx);
+			CAM_SUBDEV_MESSAGE_REG_DUMP,
+			(void *)&data_idx);
 
 		cam_ife_csid_ver1_handle_event_err(csid_hw, evt_payload, event_type);
 		csid_hw->flags.reset_awaited = true;
@@ -4286,8 +4283,7 @@ static int cam_ife_csid_ver1_rx_top_half(
 			csid_hw->hw_intf->hw_idx,
 			csid_hw->counters.error_irq_count);
 
-		if (csid_hw->counters.error_irq_count >
-			CAM_IFE_CSID_MAX_ERR_COUNT) {
+		if (csid_hw->counters.error_irq_count > CAM_IFE_CSID_MAX_ERR_COUNT) {
 			csid_hw->flags.fatal_err_detected = true;
 			cam_ife_csid_ver1_disable_csi2(csid_hw);
 		}

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -49,9 +49,6 @@
 /* Max number of sof irq's triggered in case of SOF freeze */
 #define CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX 12
 
-/* Max CSI Rx irq error count threshold value */
-#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT               100
-
 static void cam_ife_csid_ver2_print_debug_reg_status(
 	struct cam_ife_csid_ver2_hw *csid_hw,
 	struct cam_isp_resource_node    *res);
@@ -226,7 +223,7 @@ static int cam_ife_csid_ver2_sof_irq_debug(
 			csid_hw->rx_cfg.phy_sel - 1);
 
 	cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-			CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
+		CAM_SUBDEV_MESSAGE_REG_DUMP, (void *)&data_idx);
 
 	return 0;
 }
@@ -758,8 +755,7 @@ static int cam_ife_csid_ver2_rx_err_top_half(
 			csid_hw->hw_intf->hw_idx,
 			csid_hw->counters.error_irq_count);
 
-		if (csid_hw->counters.error_irq_count >
-			CAM_IFE_CSID_MAX_ERR_COUNT) {
+		if (csid_hw->counters.error_irq_count > CAM_IFE_CSID_MAX_ERR_COUNT) {
 			csid_hw->flags.fatal_err_detected = true;
 			cam_ife_csid_ver2_stop_csi2_in_err(csid_hw);
 		}
@@ -1108,30 +1104,26 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 
 		if (irq_status & IFE_CSID_VER2_RX_ERROR_CRC) {
 			event_type |= CAM_ISP_HW_ERROR_CSID_PKT_PAYLOAD_CORRUPTED;
-			long_pkt_ftr_val = cam_io_r_mb(
-				soc_info->reg_map[0].mem_base +
+			long_pkt_ftr_val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 				csi2_reg->captured_long_pkt_ftr_addr);
-			total_crc = cam_io_r_mb(
-				soc_info->reg_map[0].mem_base +
+			total_crc = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 				csi2_reg->total_crc_err_addr);
 
 			if (csid_hw->rx_cfg.lane_type == CAM_ISP_LANE_TYPE_CPHY) {
-				val = cam_io_r_mb(
-					soc_info->reg_map[0].mem_base +
+				val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 					csi2_reg->captured_cphy_pkt_hdr_addr);
 
-				CAM_ERR_BUF(CAM_ISP, log_buf,
-					CAM_IFE_CSID_LOG_BUF_LEN, &len,
+				CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
 					"PHY_CRC_ERROR: Long pkt payload CRC mismatch. Totl CRC Errs: %u, Rcvd CRC: 0x%x Caltd CRC: 0x%x, VC:%d DT:%d WC:%d",
-					total_crc,
-					long_pkt_ftr_val & 0xffff, long_pkt_ftr_val >> 16,
-					val >> 22, (val >> 16) & 0x3F, val & 0xFFFF);
+					total_crc, long_pkt_ftr_val & 0xffff,
+					long_pkt_ftr_val >> 16, val >> 22,
+					(val >> 16) & 0x3F, val & 0xFFFF);
 			} else {
 				CAM_ERR_BUF(CAM_ISP, log_buf,
 					CAM_IFE_CSID_LOG_BUF_LEN, &len,
 					"PHY_CRC_ERROR: Long pkt payload CRC mismatch. Totl CRC Errs: %u, Rcvd CRC: 0x%x Caltd CRC: 0x%x",
-					total_crc,
-					long_pkt_ftr_val & 0xffff, long_pkt_ftr_val >> 16);
+					total_crc, long_pkt_ftr_val & 0xffff,
+					long_pkt_ftr_val >> 16);
 			}
 		}
 
@@ -1151,7 +1143,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 				"CPHY_SOT_RECEPTION: Less SOTs on lane/s");
 		}
 
-		CAM_ERR(CAM_ISP, "Recoverable-errors: %s", log_buf);
+		CAM_ERR(CAM_ISP, "Partly fatal errors: %s", log_buf);
 		rx_irq_status |= irq_status;
 	}
 
@@ -1181,7 +1173,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 			event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
 
 		cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-			CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
+			CAM_SUBDEV_MESSAGE_APPLY_CSIPHY_AUX, (void *)&data_idx);
+
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
 			rx_irq_status, event_type, false, NULL);
 		csid_hw->flags.reset_awaited = true;
@@ -1520,8 +1513,9 @@ void cam_ife_csid_ver2_print_format_measure_info(
 		csid_reg->path_reg[res->res_id];
 	struct cam_hw_soc_info *soc_info = &csid_hw->hw_info->soc_info;
 	void __iomem *base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
-	uint32_t expected_frame = 0, actual_frame = 0;
+	uint32_t expected_frame = 0, actual_frame = 0, data_idx;
 
+	data_idx = csid_hw->rx_cfg.phy_sel - 1;
 	actual_frame = cam_io_r_mb(base + path_reg->format_measure0_addr);
 	expected_frame = cam_io_r_mb(base + path_reg->format_measure_cfg1_addr);
 
@@ -1539,6 +1533,10 @@ void cam_ife_csid_ver2_print_format_measure_info(
 		csid_reg->cmn_reg->format_measure_height_mask_val),
 		actual_frame &
 		csid_reg->cmn_reg->format_measure_width_mask_val);
+
+	/* AUX settings update to phy for pix and line count errors */
+	cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
+		CAM_SUBDEV_MESSAGE_APPLY_CSIPHY_AUX, (void *)&data_idx);
 }
 
 static int cam_ife_csid_ver2_ipp_bottom_half(

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/iopoll.h>
@@ -3417,7 +3418,7 @@ handle_fatal_error:
 		/* phy_sel starts from 1 and should never be zero*/
 		if (csid_hw->csi2_rx_cfg.phy_sel > 0) {
 			cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-				CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
+				CAM_SUBDEV_MESSAGE_REG_DUMP, (void *)&data_idx);
 		}
 		cam_tfe_csid_handle_hw_err_irq(csid_hw,
 			CAM_ISP_HW_ERROR_CSID_FATAL, irq_status);

drivers/cam_req_mgr/cam_subdev.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SUBDEV_H_
@@ -17,7 +18,8 @@
 #define CAM_SUBDEVICE_EVENT_MAX 30
 
 enum cam_subdev_message_type_t {
-	CAM_SUBDEV_MESSAGE_IRQ_ERR = 0x1
+	CAM_SUBDEV_MESSAGE_REG_DUMP = 0x1,
+	CAM_SUBDEV_MESSAGE_APPLY_CSIPHY_AUX,
 };
 
 /* Enum for close sequence priority */

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -46,6 +46,7 @@ struct g_csiphy_data {
 	uint8_t is_3phase;
 	uint32_t cpas_handle;
 	bool is_configured_for_main;
+	uint64_t data_rate_aux_mask;
 	bool enable_aon_support;
 	struct cam_csiphy_aon_sel_params_t *aon_sel_param;
 };
@@ -53,6 +54,28 @@ struct g_csiphy_data {
 static struct g_csiphy_data g_phy_data[MAX_CSIPHY] = {0};
 static int active_csiphy_hw_cnt;
 
+void cam_csiphy_update_auxiliary_mask(struct csiphy_device *csiphy_dev)
+{
+	if (!csiphy_dev) {
+		CAM_ERR(CAM_CSIPHY, "Invalid param");
+		return;
+	}
+
+	if (!g_phy_data[csiphy_dev->soc_info.index].is_3phase) {
+		CAM_INFO_RATE_LIMIT(CAM_CSIPHY, "2PH Sensor is connected to the PHY");
+		return;
+	}
+
+	g_phy_data[csiphy_dev->soc_info.index].data_rate_aux_mask |=
+			BIT_ULL(csiphy_dev->curr_data_rate_idx);
+
+	CAM_DBG(CAM_CSIPHY,
+		"CSIPHY[%u] configuring aux settings curr_data_rate_idx: %u curr_data_rate: %llu curr_aux_mask: 0x%lx",
+		csiphy_dev->soc_info.index, csiphy_dev->curr_data_rate_idx,
+		csiphy_dev->current_data_rate,
+		g_phy_data[csiphy_dev->soc_info.index].data_rate_aux_mask);
+}
+
 int32_t cam_csiphy_get_instance_offset(struct csiphy_device *csiphy_dev, int32_t dev_handle)
 {
 	int32_t i = 0;
@@ -929,6 +952,18 @@ static int cam_csiphy_cphy_data_rate_config(
 				cam_io_w_mb(reg_data,
 					csiphybase + reg_addr);
 			break;
+			case CSIPHY_AUXILIARY_SETTING: {
+				uint32_t phy_idx = csiphy_device->soc_info.index;
+
+				if (g_phy_data[phy_idx].data_rate_aux_mask &
+					BIT_ULL(data_rate_idx)) {
+					cam_io_w_mb(reg_data, csiphybase + reg_addr);
+					CAM_DBG(CAM_CSIPHY,
+						"Writing new aux setting  reg_addr: 0x%x reg_val: 0x%x",
+						reg_addr, reg_data);
+				}
+			}
+			break;
 			default:
 				CAM_DBG(CAM_CSIPHY, "Do Nothing");
 			break;
@@ -937,6 +972,7 @@ static int cam_csiphy_cphy_data_rate_config(
 				usleep_range(delay, delay + 5);
 		}
 
+		csiphy_device->curr_data_rate_idx = data_rate_idx;
 		break;
 	}
 
@@ -1822,9 +1858,9 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 		if (!csiphy_dev->acquire_count) {
 			g_phy_data[soc_info->index].is_3phase = csiphy_acq_params.csiphy_3phase;
 			CAM_DBG(CAM_CSIPHY,
-					"g_csiphy data is updated for index: %d is_3phase: %u",
-					soc_info->index,
-					g_phy_data[soc_info->index].is_3phase);
+				"g_csiphy data is updated for index: %d is_3phase: %u",
+				soc_info->index,
+				g_phy_data[soc_info->index].is_3phase);
 		}
 
 		if (g_phy_data[soc_info->index].enable_aon_support) {
@@ -2327,6 +2363,7 @@ int cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev)
 		csiphy_dev->ctrl_reg->csiphy_reg->aon_sel_params;
 	g_phy_data[phy_idx].enable_aon_support = false;
 	g_phy_data[phy_idx].is_configured_for_main = false;
+	g_phy_data[phy_idx].data_rate_aux_mask = 0;
 
 	return 0;
 }

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2018, 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_CORE_H_
@@ -66,6 +67,15 @@ int cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev);
  */
 int cam_csiphy_util_update_aon_ops(bool get_access, uint32_t phy_idx);
 
+
+/**
+ * @csiphy_dev : CSIPhy device structure
+ *
+ * This API updates the auxiliary settings mask for the current data rate
+ *
+ */
+void cam_csiphy_update_auxiliary_mask(struct csiphy_device *csiphy_dev);
+
 /**
  * @csiphy_dev: CSIPhy device structure
  *

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_csiphy_dev.h"
@@ -14,32 +15,55 @@
 #define CSIPHY_DEBUGFS_NAME_MAX_SIZE 10
 static struct dentry *root_dentry;
 
-static void cam_csiphy_subdev_handle_message(
-		struct v4l2_subdev *sd,
-		enum cam_subdev_message_type_t message_type,
-		void *data)
+static inline void cam_csiphy_trigger_reg_dump(struct csiphy_device *csiphy_dev)
+{
+	cam_csiphy_common_status_reg_dump(csiphy_dev);
+
+	if (csiphy_dev->en_full_phy_reg_dump)
+		cam_csiphy_reg_dump(&csiphy_dev->soc_info);
+
+	if (csiphy_dev->en_lane_status_reg_dump) {
+		CAM_INFO(CAM_CSIPHY, "Status Reg Dump on failure");
+		cam_csiphy_dump_status_reg(csiphy_dev);
+	}
+}
+
+static void cam_csiphy_subdev_handle_message(struct v4l2_subdev *sd,
+	enum cam_subdev_message_type_t message_type, void *data)
 {
 	struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd);
-	uint32_t data_idx;
+	uint32_t phy_idx;
+
+	if (!data) {
+		CAM_ERR(CAM_CSIPHY, "Empty Payload");
+		return;
+	}
+
+	phy_idx = *(uint32_t *)data;
+	if (phy_idx != csiphy_dev->soc_info.index) {
+		CAM_DBG(CAM_CSIPHY, "Current HW IDX: %u, Expected IDX: %u",
+			csiphy_dev->soc_info.index, phy_idx);
+		return;
+	}
 
 	switch (message_type) {
-	case CAM_SUBDEV_MESSAGE_IRQ_ERR:
-		data_idx = *(uint32_t *)data;
-		CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d",
-				csiphy_dev->soc_info.index, data_idx);
-		if (data_idx == csiphy_dev->soc_info.index) {
-			cam_csiphy_common_status_reg_dump(csiphy_dev);
-
-			if (csiphy_dev->en_full_phy_reg_dump)
-				cam_csiphy_reg_dump(&csiphy_dev->soc_info);
-
-			if (csiphy_dev->en_lane_status_reg_dump) {
-				CAM_INFO(CAM_CSIPHY,
-					"Status Reg Dump on failure");
-				cam_csiphy_dump_status_reg(csiphy_dev);
-			}
+	case CAM_SUBDEV_MESSAGE_REG_DUMP: {
+		cam_csiphy_trigger_reg_dump(csiphy_dev);
+
+		break;
+	}
+	case CAM_SUBDEV_MESSAGE_APPLY_CSIPHY_AUX: {
+		cam_csiphy_trigger_reg_dump(csiphy_dev);
+
+		if (!csiphy_dev->skip_aux_settings) {
+			cam_csiphy_update_auxiliary_mask(csiphy_dev);
+
+			CAM_INFO(CAM_CSIPHY,
+				"CSIPHY[%u] updating aux settings for data rate idx: %u",
+				csiphy_dev->soc_info.index, csiphy_dev->curr_data_rate_idx);
 		}
 		break;
+	}
 	default:
 		break;
 	}
@@ -86,6 +110,9 @@ static int cam_csiphy_debug_register(struct csiphy_device *csiphy_dev)
 	debugfs_create_bool("en_full_phy_reg_dump", 0644,
 		dbgfileptr, &csiphy_dev->en_full_phy_reg_dump);
 
+	debugfs_create_bool("skip_aux_settings", 0644,
+		dbgfileptr, &csiphy_dev->skip_aux_settings);
+
 	return 0;
 }
 
@@ -244,6 +271,7 @@ static int cam_csiphy_component_bind(struct device *dev,
 	new_csiphy_dev->soc_info.dev = &pdev->dev;
 	new_csiphy_dev->soc_info.dev_name = pdev->name;
 	new_csiphy_dev->ref_count = 0;
+	new_csiphy_dev->current_data_rate = 0;
 
 	rc = cam_csiphy_parse_dt_info(pdev, new_csiphy_dev);
 	if (rc < 0) {

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_DEV_H_
@@ -51,6 +51,7 @@
 #define CSIPHY_2PH_COMBO_REGS            7
 #define CSIPHY_3PH_COMBO_REGS            8
 #define CSIPHY_2PH_3PH_COMBO_REGS        9
+#define CSIPHY_AUXILIARY_SETTING         10
 
 #define CSIPHY_MAX_INSTANCES_PER_PHY     3
 
@@ -308,6 +309,7 @@ struct csiphy_work_queue {
  * @cphy_dphy_combo_mode       : Info regarding 2ph/3ph combo modes
  * @rx_clk_src_idx             : Phy src clk index
  * @is_divisor_32_comp         : 32 bit hw compatibility
+ * @curr_data_rate_idx         : Index of the datarate array which is being used currently by phy
  * @csiphy_state               : CSIPhy state
  * @ctrl_reg                   : CSIPhy control registers
  * @csiphy_3p_clk_info         : 3Phase clock information
@@ -324,6 +326,7 @@ struct csiphy_work_queue {
  * @en_common_status_reg_dump  : Debugfs flag to enable common status register dump
  * @en_lane_status_reg_dump    : Debugfs flag to enable cphy/dphy lane status dump
  * @en_full_phy_reg_dump       : Debugfs flag to enable the dump for all the Phy registers
+ * @skip_aux_settings          : Debugfs flag to ignore calls to update aux settings
  * @preamble_enable            : To enable preamble pattern
  */
 struct csiphy_device {
@@ -340,6 +343,7 @@ struct csiphy_device {
 	uint8_t                        cphy_dphy_combo_mode;
 	uint8_t                        rx_clk_src_idx;
 	uint8_t                        is_divisor_32_comp;
+	uint8_t                        curr_data_rate_idx;
 	enum cam_csiphy_state          csiphy_state;
 	struct csiphy_ctrl_t          *ctrl_reg;
 	struct msm_cam_clk_info        csiphy_3p_clk_info[2];
@@ -358,6 +362,7 @@ struct csiphy_device {
 	bool                           en_common_status_reg_dump;
 	bool                           en_lane_status_reg_dump;
 	bool                           en_full_phy_reg_dump;
+	bool                           skip_aux_settings;
 	uint16_t                       preamble_enable;
 };
 

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_2_1_0_HWREG_H_
@@ -452,6 +452,7 @@ struct csiphy_reg_t datarate_210_1p2Gsps[] = {
 	{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0A14, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x108C, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x108C, 0x00, 0x00, CSIPHY_AUXILIARY_SETTING},
 };
 
 struct csiphy_reg_t datarate_210_1p5Gsps[] = {
@@ -477,6 +478,7 @@ struct csiphy_reg_t datarate_210_1p5Gsps[] = {
 	{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x108C, 0x00, 0x00, CSIPHY_AUXILIARY_SETTING},
 };
 
 struct csiphy_reg_t datarate_210_1p7Gsps[] = {
@@ -502,6 +504,7 @@ struct csiphy_reg_t datarate_210_1p7Gsps[] = {
 	{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0A14, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x108C, 0x00, 0x00, CSIPHY_AUXILIARY_SETTING},
 };
 
 struct csiphy_reg_t datarate_210_2p1Gsps[] = {
@@ -527,6 +530,7 @@ struct csiphy_reg_t datarate_210_2p1Gsps[] = {
 	{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x108C, 0x00, 0x00, CSIPHY_AUXILIARY_SETTING},
 };
 
 struct csiphy_reg_t datarate_210_2p35Gsps[] = {
@@ -552,6 +556,7 @@ struct csiphy_reg_t datarate_210_2p35Gsps[] = {
 	{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x108C, 0x00, 0x00, CSIPHY_AUXILIARY_SETTING},
 };
 
 struct csiphy_reg_t datarate_210_2p6Gsps[] = {