DW9784 needs Big endian type when QTime is written
into registers.
CRs-Fixed: 3359195
External Impact: No.
Change-Id: I6c141de255dbedb933ca5529f5ce4562d93a7c3a
Signed-off-by: Yulei Yao <quic_yuleiy@quicinc.com>
This change will help to give information on camera cesta current clk
operating level.
CRs-Fixed: 3327242
Change-Id: I0422d557985b1044fcd9bab2ce201b8c21e4e295
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
External dependency has been reverted, change not ready.
This reverts commit b76d66be06cb035886ddebbf7671e02c93fdd1af.
CRs-Fixed: 3317248
Change-Id: If82504f1eb22b1c908d08d256f3b4c4cbad60bc9
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
In current code, composite done values are stored as shift values and
converted to mask in the driver logic. This causes redundant operations
in the code as the masks are static values.
This commit replaces the bit shift values with masks so that they
can be converted at the compile time thereby reducing some CPU
execution cycles during start and IRQ handlers.
CRs-Fixed: 3321317
Change-Id: I1507b4dbee4855ad866f69ed16b0b9dafe0a4e99
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Due to i2c driver remove call return value changed from int to void
from 6.1 kernel version.
CRs-Fixed: 3366233
Change-Id: I81713fdd65a53af37b0b9c573407587755bc1bae
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
During probe, each hw mgr register as a client to HFI layer and share
the handle to icp core layer to book keep. HFI register routine searches
for a free hfi slot to dynamically allocated hfi info struct and returns
a client handle to the caller. During open sequence, HW mgr is required to
initialize the hfi using the handle obtained from the registering in boot
up. Upon unregistering, the hfi slot and the hfi info memory is freed.
Hw mgr layer can invoke the existing hfi interfaces by passing hfi handle
to fetch the right hfi info. With this change, each hw mgr can
independently run on one HFI to interact with FW.
Add support in enabling OFE PC and config OFE UBWC in hfi layer, and parse
OFE UBWC config values from DT.
CRs-Fixed: 3338951
Change-Id: Iec2358fef124e9c169d06df79ce31b65a9b80d40
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add OFE device allocation and initialization. Verify number
of DT listed devices with cpas capability. Create common
sets of command types for IPE/BPS/OFE. Refactor the current usage
of IPE/BPS device interfaces to scale to n number of devices
including OFE. Add support for OFE functionality: acquire/
release, init/deinit, PC/Resume, get gdsc, clock update,
OFE HFI commands and message handlers.
CRs-Fixed: 3337784
Change-Id: I94c9bd21cf21dead6733c7cd6b86e343e86169de
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add OFE stream type(rt/nrt/semi-rt) to be used for hw acquire,
add ofe setting/update opcode for preparing hw update, add
ICP/OFE dev type for query cap v2 usage, and a new macro
to define the max number of device types supported by ICP instance.
Remove usages of deprecated max macros - CAM_ICP_RES_TYPE_MAX
and CAM_ICP_DEV_TYPE_MAX in the driver.
CRs-Fixed: 3336554
Change-Id: Icf27958571f6e31896539d0cd692e0e7a67c5cd8
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
To enable multiple HW MGRs, static icp hw mgr is an array
and no longer a singleton object. The hw managers share the
same function routines; thus, routines that assume singleton
hw mgr are changed to support input parameter hw mgr. Different
hw mgr has separate sets of hw ctx, clk/bw info, workq, iommu hdl
, hw intf, WD, debugfs, locks, etc. So, They can run simultaneously
and independently of one another.
Before hw mgr initit/deinit, map corresponding icp subdevice to
hw mgr based on cell index in DT.
Each hw mgr has its own debugfs that can be interacted by users
independently of others.
CRs-Fixed: 3336534
Change-Id: I1ac5e244c5219c2e8f0c46f44e9a8ba6da16cf99
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
UMD can send packet with READ or CONFIG opcode with req
id 0, if we update the last updated req for every packet,
then the res info may be updated incorrectly. This change
updates the last updated req only when there are valid
res info updating.
CRs-Fixed: 3359553
Change-Id: Ia08ccf7683b87378d00a5ae41e189a70a01cc0fc
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Adds support for new mink call to configure secure
camera sessions. This new mink call takes in additional
parameters to support the new domain-id based
security scheme. The additional parameters are in the
form of csid_hw_idx_mask, cdm_hw_idx_mask and
vc_mask. These are in addition to the existing PHY idx
and CPHY/DPHY lanes info.
The introduction of this new mink call deprecates the
existing SCM call used to service secure camera sessions.
What this means is that on all subsequent versions of this
driver, all secure camera sessions will be serviced by this
mink call, which is able to accommodate older and newer targets,
and their programming of different register sets.
This design enables the cam_csiphy_notify_secure_mode
wrapper to remain the same, with the underlying mink call
made in the cam_compat layer, depending on camera driver
version.
CRs-Fixed: 3317248
Change-Id: I575f4b85097c81f047f398216d0190b249e6b200
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
Add support to map global sync and hw mutex memory for ICP.
Share the region information with FW over GP registers.
CRs-Fixed: 3351015
Change-Id: Ie7a6af40ffd922ae89d64205787e3c656a007c49
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add support to have multiple same regions, and each region can
now support different subregions.
CRs-Fixed: 3351015
Change-Id: I733cce9c2c571ff21860871c5efdb19e833b1238
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
This commit refactors the ISP packet parser APIs to remove
the loops based on resource and split ids. This saves
the renundant iterations.
It also breaks some big functions into small util functions.
It allows the code to be more modular and can be used from multiple places.
Removes lot of duplicate code as well.
CRs-Fixed: 3321317
Change-Id: Ifdfd13387c6e70cae40b0ef4a675bca8121c548d
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Update validation checks to ensure copy from user does not
go beyond assigned memory. The change also adds dma fence ref
count prior to signaling sync object.
CRs-Fixed: 3327260
Change-Id: I9e2a57ecd686d2b9125789f7532812de647af7a5
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
This commit prints the event record at the time of
LDAR. This commit gives information about the
last 8 events of request Submit, Apply, Epoch,
Reg Update and Buf Done.
CRs-Fixed: 3321317
Change-Id: I8d83f2b1ea0ccabc615a679489816e52ac6f00a4
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Unify the name of scratch buf_done function of IFE and SFE
CRs-Fixed: 3334207
Change-Id: I784e87fbf0955e191c7b08b254da3635bc0a6d72
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
camera-kernel:
0cae312 Merge "msm: camera: common: Add support for cesta based clk scaling" into camera-kernel.lnx.dev.
Change-Id: I2d84ead77dd6c53385726fa6b11c5646d145e3ff
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
camera-kernel:
4fa62d9 Merge "msm: camera: isp: Do internal recovery when meets back to back bubble request" into camera-kernel.lnx.dev
580d5b3 Merge "msm: camera: isp: UAPI changes for Spectra v980" into camera-kernel.lnx.dev.
Change-Id: I474d9fd7efa3570de845d23e5d9851ee59f953a0
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
On chipsets having cesta hw block support, for cesta supported clks
clk frequency can be changed during veritcal blanking based on
CSID DRV events. For this to happen, camera clients need to setup
high and low clock votes through hw clients. Use corresponding clk,
crm APIs to setup high, low clk frquencies and do channel switch
to apply newly set rates. Clients can also set clk frequency through
sw client which will set the floor. This feature helps in saving
power for usecases where vertical blanking is high such as
Fast Shutter usecase.
CRs-Fixed: 3294948
Change-Id: I1bcf650b439991a23b2a0f0f9a5162bdcd60dc64
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Do internal recovery when a request meets back to back bubble.
CRs-Fixed: 3300029
Change-Id: I6b2dc3bffd5cd624cd3b32f3c5c96134e2120d06
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
Each driver can pass private data in mini dump callback register, so
when mini dump is invoked, the mini dump handler will pass the private
data to the callback associated with the driver. With the private data,
ICP driver can determine which mini dump callback corresponds to which
ICP device/hw mgr.
CRs-Fixed: 3353541
Change-Id: I85171aa7ba31f92c5620ddbd8de8a9c168398856
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
This change adds bubble update packet support, when the
sensor mode or feature mask of bubble req is different
with last applied, we can use bubble update packet to
recovery the sensor mode and feature, then the bubble
req can get frame from correct sensor mode and feature.
CRs-Fixed: 3317352
Change-Id: Ia80b578044e74cc5062f9f6c12c5ae8edd2049ac
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
camera-kernel:
bcd8dba Merge "msm: camera: icp: Remove input/output fence dependency" into camera-kernel.lnx.dev
a59199e Merge "msm: camera: icp: Support multiple ICP subdevices" into camera-kernel.lnx.dev
cce6feb Merge "msm: camera: sync: Update global synx property" into camera-kernel.lnx.dev
ae06a1d Merge "msm: camera: cpas: Fix cpas query cap log" into camera-kernel.lnx.dev
d4f8bd8 Merge "msm: camera: ois: Update ois state correctly" into camera-kernel.lnx.dev
aee4d47 Merge "msm: camera: isp: Add top irq mask for csi rx of csid lite" into camera-kernel.lnx.dev
76f56a5 Merge "msm: camera: isp: Don't report bubble if req is applied after SOF" into camera-kernel.lnx.dev
bf80a9e Merge "msm: camera: cci: Make cci can be realesed when cci status is negative" into camera-kernel.lnx.dev
5554fcb Merge "msm: camera: isp: Reset the out of sync count" into camera-kernel.lnx.dev.
Change-Id: Iba843f4f61c56b799821ced879e01106661ce429
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
Add infrastructure to allow multiple ICP subdevices to co-exist
with each subdevice exposed to UMD individually. All operations
including ioctl on each subdevice are discrete from another's. Add
a new private field in node structure to point to which subdev
the node belongs to. Add a new ICP1 device type and expose the type
associated with ICP1 to userspace for identifying the second ICP.
Each subdevice's unique name is derived from "cam-icp". The name is
then appended with a cell-index if it exists. If there are multiple
nodes in DTSI to be probed, each node must contain cell-index to
differentiate them.
For each subdevice, it is expected to have a unique node in DTSI
with unique compatible string to probe the sd during boottime.
CRs-Fixed: 3336505
Change-Id: I615f9489d5f22b0ec37f98be3fec4c67b06a52d0
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Set ois state to config state only after init settings is
applied successfully, to avoid sensor power down is called
twice while init settings apply fail.
CRs-Fixed: 3332288
Change-Id: Ifdd407ea3c07eafc4091e2df354bc704ba6f0f7c
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Currently all synx handles need to be global. Update
synx create params accordingly.
CRs-Fixed: 3351015
Change-Id: I58d6f927b5a7c1508a34a64c916ca3c9fbb1de49
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
It is possible for UMD to send synx handles directly to FW
for input or output. FW will signal these fences to CPU.
On such occasions, ICP HLOS driver can skip processing
input and output synx fences. Synx will signal CSL.
CRs-Fixed: 3351015
Change-Id: Ia2c36db3bdaf75e12e27484357350fb20f32fcbc
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
If use csid lite, the csi phy rx irq doesn't set correct top irq
mask value while register dependent, and if error happens on csi
phy, we cannot stop csi rx and disable irq lead to irq storm and
phone crash.
CRs-Fixed: 3339444
Change-Id: Iae2fe4c40959b913959445a6f1631b7acf48b4af
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Reset the out of sync count once VFE can get valid
SOF irq.
CRs-Fixed: 3311867
Change-Id: I1671cb03616fba89597e2fe7d2d37c310fa20102
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Make MSM_CCI_RELEASE command can be executed even if CCI status is
negative. When IIC meets NACK error, CCI status will be set to
negative state. But in function cam_cci_core_cfg, if CCI status is
negative, then the command will not be executed, and the return value
of function camera_io_release is never checked, so we do nothing
even if cam_cci_release is not executed, if all MSM_CCI_INIT cmd
is executed successfully but one or more MSM_CCI_RELEASE cmd is not
executed, the streamon_clients of cpas will never be reduced to 0
and cpas will never be powered off.
CRs-Fixed: 3316756
Change-Id: I7f3d8d4e604f5a41983f1419ccc8b5817b199740
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
We may apply req in between SOF and EPOCH due to workqueue delay,
then we will apply default setting in same frame, it will cause
the buf done of the following frame is delayed one frame in SHDR
usecase. This change avoids to report bubble for that case.
CRs-Fixed: 3325004
Change-Id: I1a3ae198466fde6390245a55f0f695649741bd62
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
As per current code, csid rx side phy_sel is indexed from 1 but on
csiphy side we consider indexing from 0. So, while notifying csiphy
we need to do correct scalling. This change will fix uncheck subtraction
by adding parameter in target files which will take care of any base
used for phy selection.
CRs-Fixed: 3314104
Change-Id: I4294830a099417b944406171348aae497c41611c
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
Increase max sync handles that can be created per
camera synx session to 256.
CRs-Fixed: 3343701
Change-Id: I5c02e6693056df302d1c0fe7005f3278ae752f45
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
