Add dsi ctrl version 2.7 and dsi phy version 5.2 support for
Kalama hardware.
Change-Id: Ia7b4c8a2e1579458f114e466de8b24855e9251ce
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Changes include support for specific DP PHY
registers and related code changes for 4nm
target.
Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.
Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
Extend the existing sys_cache_enabled debugfs node functionality
to enable/disable all the display related system cache. Boolean
property is converted to integer and each BIT is associated with
a system cache.
Usage:
enable SYS_CACHE_DISP:
echo 1 > /d/dri/0/debug/core_perf/sys_cache_enabled
enable SYS_CACHE_DISP_WB:
echo 2 > /d/dri/0/debug/core_perf/sys_cache_enabled
enable both:
echo 3 > /d/dri/0/debug/core_perf/sys_cache_enabled
Change-Id: I41eaacc4d3f448bb566993b20aa74caa979f1258
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a cache_flag in msm_fb object to store the system cache state hints.
Writeback connector will store cache write hints if system cache write
is enabled while HW is writing into this buffer. Plane in the primary
display path, in a 2-pass composition strategy will use this cache hints
to enable the display HW to use system cache for reading the pixel data
from this buffer.
Change-Id: Iff92a453a36d4a60b5a0162832eebd5e8739b5c3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a custom cache_enable property in writeback connector to allow
user-mode to control the cache setting on a frame basis. Configure
the hw and activate/deactivate the llcc based on the property. The
custom property is added based on the availability of the system
cache for writeback.
Change-Id: I812b31955eb36c75c33ac279b56502a13f7cdcbf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add support to enable writeback block to use system cache for writing
the output buffer. This is useful in cases where output is routed to
primary source pipes with 2-pass composition. The implementation is
modelled based on existing pipe based cache configuration.
Change-Id: I2b9a96c5b42eb5727d11ca0f337aeeb4e69362c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 9.x, the pp-done wait requirement as part of autorefresh
sequence is not required. Add a catalog flag to avoid the wait for
mdss 9.x+ and to support backward compatibility.
Change-Id: Ieca008d3d6ef0f7326b65433ef42ed9f49a94f87
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The interface resolution can be different from crtc/layer-mixer WxH
when certain features like destination scaler are enabled. Use the
sde_crtc_get_width/sde_crtc_get_mixer_width functions throughout
to get the correct crtc/lm size based on different features enabled.
This will help in validating/configuring lm & plane correctly.
Change-Id: I45de5844bf7465a3389cf723479c5449a835fb0a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add support to read and clear the ubwc error status for wirteback.
Log the status during writeback timeout cases to help in debugging.
Change-Id: I11f3827d4a88565b81b21b651971cec55ba06298
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a writeback connector property EARLY-FENCE-LINE to give usermode
the control on when to trigger the retire fence. This option is useful
in 2-pass composition, where the writeback triggers the retire-fence
early based on the prog-line which allows primary to start the fetch
before wb transaction is fully completed. This helps to keep the clks
and bw low. WB hardware generates the line-ptr-irq when wb output reaches
the configured prog-line. Retire fence is triggered based on the irq by
default and wb-done handles for cases where line-ptr-irq is missed.
Change-Id: I20867979693dc3447f77da24cd7e88305947fb6d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 9.0, writeback supports a programmable lineptr support, which
generates an interrupt when the configured writeback output height is
reached. Add software support to configure the prog_line and to process
the interrupt.
Change-Id: I3293ad2984c51417e4691c5b11e9c9a010067e1c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently, writeback frame-triggers are serialized by default. Add
logic to support the different frame-trigger modes which can be set
through the connector property or encoder debugfs node.
- default: waits for frame(N-1) completion (wb-done-irq) before
configuring current frame(N) and releases the commit-thread on
frame-start (ctl-start-irq)
- posted-start: no previous frame(N-1) completion wait. Configures
frame(N) and releases the commit-thread on frame-start (ctl-start-irq)
- serialize: no previous frame(N-1) completion wait. Configures frame(N)
and releases the commit-thread on frame(N) completion (wb-done-irq)
(wb-done-irq) before configuring the next frame.
Restrict wb posted-start support only for MDSS 9.x+ targets, with older
targets defaulted to default-mode.
Change-Id: Id441378fd79ecbfcfb820da1ff23b14ccfd8e798
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add ctl-start-irq support which serves as an indication the
HW read the current frame's configuration and software is free
to program the next frame.
Change-Id: I9f6b180cf9e47894ca81d2d4b6ac724827d1368c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently, cwb disable path issues a cleanup flush & waits for the
commit-done. Wait for the tx-done to ensure the transfer is complete.
Change-Id: I509711c157f1d6646646ad96ed140d6bc76d2dba
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Avoid drm vblank on/off for virtual displays to allow drm framework to
ignore the vblank requests. Vblanks are unnecessary for writeback as it
is triggered based on the frame-updates and not on any defined interval.
In addition, avoid vblank callback registration for concurrent writeback
encoder.
Change-Id: I205734e2e3076469dc7f775566cf5e104bac4082
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Remove the hw feature flags that are set by default for writeback as
it does not add any value. As part of the change, remove the unused
wb register offsets.
Change-Id: I04376242e764d8d0a1edb763c9f799d7ae5447ac
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Remove the writeback kickoff_count/frame_count & start/end time
logging. These are redundant counters used for debug purpose. The
pending_retire_fence_cnt and event-logs timestamp can be used for
this purpose. Remove the bypass_irqreg flag as well as its not used.
Change-Id: I1644325afc214f75c76baad615da90c8114836cc
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Expand various SSPP and CTL related data structures
to support DMA 4,5.
Change-Id: I0ce052b6a2f1599a9b6eb82ce8e4f34f4c68333d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
From Kalama onwards, the VBIF CLK_CTRL register has been moved from TOP block
to individual hardware block memory range.
This change is adding a backward compatible solution to support
per block VBIF CLK_CTRL access by allowing each HW block to register
set of callback ops. Additionally, it adds DMA and IPCC/MSI VBIF CLK_CTRL
block type.
Change-Id: Ia82ced34cfa1636b57cd1c03b327faf923be482a
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.
Change-Id: If7655e4eae351bac248f0906c473cdfaf93f2b8a
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Based on panel hardware support, display brightness levels can
be very high value. This high value display brightness cooling
device levels can cause exceeding PAGE_SIZE for cooling device stat
buffer. It leads to buffer failure for cooling device stat feature.
Limit display panel mitigation level max to 255. If hardware
supports more than 255, then scale brightness levels fit
into above limit.
Change-Id: Ieeee4ff2aa5cd884819b30b4fd9839e48ac4d804
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Add DSCv1.2 native 422 format with 10bpc and 8bpp config
and format specific fixed rate control parameter table
entries as per the systems recommended settings.
Change-Id: Ibd1a5203be2c59f4699537a31f9ae6d69bcfe5ab
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change enables support for wb1 in ctl path and
adds irq support.
Change-Id: Iebbe35725aa279b8e02217ea93ba1b481f5e869f
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change deprecates idle notify work for video mode
since idle timer will be maintained by userspace.
As part of idle notify work, syscache state is changed from
CACHE_STATE_NORMAL to CACHE_STATE_PRE_CACHE along with
notifying to the userspace. This change removes
CACHE_STATE_PRE_CACHE in the state machine and state is
updated from CACHE_STATE_NORMAL to CACHE_STATE_FRAME_WRITE
whenever the cache property is set.
Change-Id: If3b2c34be954cb625aca76da81fd854c077a8250
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
If there are any uncleared DP interrupts before deinitialing
and turning off the clocks, the interrupt might get stuck at
the MDP level and can't be cleared without turning the DP
clocks back on. To avoid this situation, this change clears
all the interrupts before turning off the clocks.
Change-Id: Id13b102fa81c85f92ae8c1d11ffaf7d5bad5fd12
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Add check to clip the sunlight visibility scale to an upper limit of
MAX_SV_BL_SCALE_LEVEL * 4.
Change-Id: I8cc7bf8fba90e115d046ec030983801ce6d93c1d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
HDCP authentication has strict timing requirements and if the
display is on static screen during this time, it is possible
that SDE removes the QOS vote when it detects static display,
thereby affecting the hdcp authentication process.
This change adds qos support in dp driver to vote exclusively
for DP. If valid QOS settings are provided in dtsi, then the
driver adds the vote when it starts authentication and removes
the vote when authentication is completed.
Change-Id: I1d8bc098d0857b13fdf1ca089b6dd2d3f381bdb8
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During an HPD, HDCP IRQ handler prints error log and exit
if HDCP state is inactive or authentication failure.
Inactive state is a benign error and auth failure will be
reported by hdcp kernel module. This change will downgrade
this error log to debug log.
Change-Id: I2a64e3c94a6661db70e93d07f5e3608202fe8871
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
During a probable race condition where usermode is triggering
a delayed cleanup, this instance would be empty leading to a null
pointer dereference. This change will add protection around this
pointer.
Change-Id: I8e90a1ba3ca925f08678e5fa67616420204edae7
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Considering requirement for supporting panel refresh rates upto
1Hz current default timeout value is not sufficient. Based on
panel refresh rate update vsync wait timeout value so that
any vsync waits from here on will have adjusted timeout value.
Change-Id: I65af152c4bd3decdd7135a4cc38f54e3bb3d5c92
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
With requirements to support an increased number of display modes,
the current size of sde_kms_info is insufficient. This change
increases the sde_kms_info max size.
Change-Id: Ie0f29003732870dad9ce31ee7d484e84f12ba542
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
