Reinit thread priority work before queueing on multiple display
threads as the work stores the former worker thread. Also
flush work such the next init is serialized.
Change-Id: I51409d4d12d100be0cb30238f812a56ec064a339
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add HW recommended programming sequence for when PHY is allowed to turn
off during idle.
Change-Id: Iaeafa17d9821913b42ae669dbd21f244783f4cdd
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change adds the new files for DSI PHY version 5 and 4nm
DSI PLL.
Change-Id: I97712d6ce53a60a6fae1c8331b6ba9a5d17b8d34
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
During the first commit, crtc state will be duplicated from the
crtc state populated with splash data. In this case, crtc will
already be set to active, but active_changed will remain cleared.
This will skip the power on event being set during complete commit
phase. This change checks for the cont. splash enabled before
sending the power on event.
Change-Id: I9964317d96468213e9abe9b029e64aa2981fb359
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the cwb block offset and stride values for kalama
target in sde hw catalog. As part of the change, allow the
ctl wb-flush bit for cwb to be set based on the wb idx used.
Change-Id: Ibf7ccda88cbb47bddacf53b5af9841d381a4766c
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
From kalama, add support for QoS fill level calculations based on
line-based QoS calculations.
Change-Id: I524ca29c6e9d1912b44a328a2a88d08341cccefc
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.
Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the sde HW catalog parsing to get separate values for rp_remap
and lvl_remap for each qos level. Previously, only rp_remap were provided
and the same was applied for lvl_remap. As part of the change, add cnoc
remap level which is added as part of MDSS 9.x.
Change-Id: I112a715f8b33cd4b028886d8074e35fef75b8aab
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the DT parsing logic to get danger/safe LUT values for
both portrait & landscape for all the usage types.
As part of the change, fix the correct CDP write setting for
CWB usecase.
Change-Id: I4fb6d17537de5df31c9b7f52983c0c3890265174
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently ot limits are being set for concurrent writeback,
which is not supported. This change adds a check to correctly
set wfd parameter while applying ot limit settings.
Change-Id: I87c1ca756c1714fec4466cd5a5a820ddf2519975
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, CDM usage is restricted to WB2 and INTF3. Expand the usage
to all writeback blocks. However, CDM is a single HW block and can be
used by only one interface at any point of time, which is controlled by
the sde_rm reservation.
Change-Id: I9fc892046e5df6c1d4d74ca410bf48053136a1ca
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.
Change-Id: I9c55f5da2037cb8c448cc978eac0a04608a93650
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Large allocations using kzalloc can lead to timeouts. This updates
the allocation calls accordingly to use vzalloc to remove
requirements on contiguous memory.
Change-Id: I86fa0ae13277d97477210a082703514df792d8a9
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
With full DSC size of 20k, RT performance issues are seen due to the
stress created during larger prefill needed to fill up the 20k DSC buffer.
Limiting DSC size to 10k helps to mitigate these RT performace issues.
This change adds support for this based on new flag has_reduced_ob_max
in sde_mdss_cfg data structure. Flag has_reduced_ob_max has be set
true only on targets where its recommended.
Change-Id: I649d213bcd378025bd0548fb982b55c98c99224f
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change adds pp_tx during DMS switch for sim panel to
prevent WD timer getting updated in middle of the frame and
creating early vsync which might result in ppdone timeout.
For non-sim panels, this tx wait is not required and is
done similar to posted start.
Change-Id: Ifec68535efa19df27e651ce0a39c03627dff2089
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.
The change adds a check for pending queued commands before any force
update of DSI clocks.
Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
In mid and low tier targets there is reduction in pingpong
blocks and static allocation of pingpong blocks with respect
to dedicated cwb ids causes mismatch failures and leads to
wb kickoff timeouts. This change corrects the pingpong block
id allocation for dedicated cwb in dither control register
programming path.
Change-Id: I98c06a2c3b49c7ea0556dcf1a921969c300fed16
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change avoids setting of max vblank count in crtc
enable if accurate vsync timestamp feature is disabled.
Change-Id: I6d8299359f581a162a7412da8c9b673e3aeae041
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Below is the sequence during which issue is observed
while using stale lut values:
1) Scaler block is enabled in the VIG pipe along with the
valid lut configuration.
2) Idle work gets scheduled and GDSC is turned off erasing
the saved lut values.
3) At the same time, userspace sends a commit assuming lut
values are still valid resulting in artifacts on the
screen.
In the plane state scaler config, only lut flag will be
reset for subsequent commits and remaining properties such
as filter cfgs, lut_idx etc. remains same. This change
caches the lut flag in sde plane whenever the lut is being
set and reuses this flag to handle above issue.
Change-Id: I7d83d5e7a22a73a2d94b100dffe60316f92ec309
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change sets kms in msm_drm_private to NULL during
msm_drm_unbind as this can be accessed from msm_lastclose
during msm_pdev_shutdown concurrently.
Change-Id: Ic44f5cf88a96c970903f2c7d3c5b627e22b411fc
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
During DMS, when tear check registers are updated near
rd_ptr line count, it was resulting in a spurious
rd_ptr_irq to which frame is getting latched and causing
tearing on the screen. This change updates
TEAR_SYNC_WRCOUNT register before disabling the vsync
counter and adds a spinlock to avoid pre-emption.
Change-Id: I986dc3ce6fb3da5fed758c2f50562df44f2ab557
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
At present, idle_pc_enabled flag will be set for encoders
containing only these capabilities MSM_DISPLAY_CAP_CMD_MODE
and MSM_DISPLAY_CAP_VID_MODE. When cwb is triggered,extra
power vote will be taken during kickoff and vote remains
till cwb is disabled. In between, if primary goes into idle
power collapse, vote taken by cwb will not be removed since
idle_pc_enabled flag is not set. This change updates
idle_pc_enabled flag for all encoders based on catalog
property.
Change-Id: If4f147edbd610d0302e4d6c0a3e6b7de2c729db1
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Keep posted start as default configuration in driver
if SBLUT is supported on target.
Do not allow HAL to override driver's default frame trigger mode.
Change-Id: I46ad5c87abfb05446592b0e497a23a3a3fc62ca7
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Flush ESD status work before resetting the encoder state during
virt_disable sequence to avoid stale pointers being used in
the ESD work.
Change-Id: I4bb08a7a7ae33ad6386169667692736e554141c4
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
This change allows concurrent qsync updates along with
DMS modeset condition. With this change, qsync can be
enabled or disabled in the same atomic commit along with
MSM_MODE_FLAG_SEAMLESS_DMS condition.
Change-Id: I1b51a68f947126b25a578645e92d95c9a8ae26f5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines and prefill lines specified
from the panel timing info.
For panels with higher porches exceeding default prefill lines
alternate framedrops can occur if transfer-time exceeds RSC static
waketup time as actual prefill lines are considered in RSC static
wakeup timer calculation. This change ensures transfer-time is with
in RSC static wakeup time.
Change-Id: I3663f9c9179efb7225a748f456f2a2cf167d241e
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Ensure register write is complete with a write barrier
while disabling other vbif debugbus when not in use
and also while clearing the test point.
Change-Id: I40da69027f86e13f4a71d87ad3975f94a5a1cb31
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
When a new connector is added or removed an a crtc because
of clone mode enable and disable update cached encoder mask.
Currently since cached encoder mask is not updated properly
vblank frame counter is returning wb encoder frame counter
right after clone mode disable on wb encoder.
Change-Id: Ieff9dfbf0c7df3688fb1b6f9d3f3614345b494c2
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
