This reverts commit 14e7e9b409346aa77fd08cca6eab85252d9ccabe.
Reverting this for now until we properly understand the reason
for command transfer timeouts that we are hitting for 5k panel.
Change-Id: I0390af66f9ca06abc1ebb81996bb683dea35beac
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change adds a debug node named 'crc' to drm_dp to read
the frame CRC values for DP controller and DP Sink. In order
to facilitate the immediate read of the CRC values when
accessed, it enables the CRC calculation on the controller
and sink automatically when the stream is enabled. In addition
to the frame CRC values it also reads the MISR values from
controller and PHY to validate the data flow from controller
to PHY.
Change-Id: I1acee2dba931e4635caf4a400e336a72c86e88bf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Use with the new connector state during validation phase for
checking the 3d-merge topology, since this is the state that
needs to be validated.
Change-Id: Ie212f948affa4dc439ef508363bac6713e560006
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
MDSS 9.0.0 supports 10 pipes, so modify the max_planes
accordingly. This is used for the frame_data transfer
between user/kernel and since its a new feature added
there is no backward compatibility that needs to be handled
for this uapi change. Add corresponding bound check during
the usage.
Change-Id: I0853fcc55395855d798f2c1b03cf9bf7b4bd3c96
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change skips msm_lastclose, when splash enabled builtin-displays
equals number of actual displays and are stuck in continuous splash.
It fixes the issue seen with change commit 548b17185e95
("disp: msm: send power_on event in dual display composer kill scenario").
Change-Id: I1f5417d8945db621dc20ab0a9cc0146eabae5e22
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This patch cancels all the delayed_off_works if scheduled and flushes
the display threads for completion during msm_lastclose. The commit
from msm_lastclose client modeset to disable any crtcs if enabled is
always scheduled on primary crtc_commit thread. In the current issue,
delayed_off_work is scheduled on secondary display crtc_commit thread
and primary crtc_commit thread is scheduled to turn off active crtcs
from msm_lastclose leading to null dereference access of sde_enc's
cur_master. This race is avoided by serializing the operations in
msm_lastclose.
Change-Id: I30cc95b925c8134f0064816ebe2cfdb86a49fb36
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently, driver is determining the amount of memory to allocate
based on the event log object indexes (first, last). The last index
can change if there is additional logging done during the coredump
phase and potentially cause an out-of-bound memory access during
buffer traversal.
This change restrict the event log object traversal to a maximum
of the output buffer size.
Change-Id: I91e5734362d2d7a796129fce85e27611bab2245f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.
Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Avoid shutting down DSI PHY and lanes before entering into
idle collapse.
Change-Id: I62fb40c2398e544b08b8cb8788ac2dc1143a82ce
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
DSI PHY has various resets defined to reset analog, PLL and digital
portions. In current sequence, these resets happen after PLL is locked
which can result in introduction of jitter on PHY lanes.Reordering these
resets to happen before PLL is programmed to have intended clean start
of DSI PHY.
Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3e8269febe3ed6e55ac9381a8de35e7d19fa3160
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change converts the ubwc stats roi into a blob property. This
allows for the roi data structure to be passed into kernel.
Change-Id: I4b30dcc16bcbd152428861444ff321add860942f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Currently, dnsc_blur hardware block is not updated when the connector
dnsc_blur property is set to NULL or when dnsc_blur_count is 0. Update
the dnsc_blur hw block configs to avoid stale configs affecting the
current frame.
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Change-Id: If64dc5548b03edba401fb7f40edf3419dbe57ca3
Change the debug message to error during the writeback
encoder validate for wb output buffer. The output buffer
can be NULL only during disable frame and all other frames
need to have a valid output buffer.
Change-Id: I4d6fecfeaf863e56fe25e17ab1200849003b3309
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently regdump framework for all the DP domains are registered during
init. But, unlike other modules in DP each SWI module is controlled by
its own clock and cannot be read without turning on the corresponding
clocks. Trying to do so might lead to unexpected behavior. This change
removes registering these nodes.
Change-Id: Ib20d7212bde24f3858558009e1679661731d16df
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
When spr and demura init config function pointers are not null,
then only enable those features. For secondary panel in dual display
for trusted ui, these features will be disabled.
Change-Id: Idcbc672d9da62664bdbaa9489dbfac9f6ab80ec1
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
During MST scenario, plugging out all the downstream monitors connected
to the MST hub would trigger a disconnect handler which would cleanup
display structure. This isn't required since MST hub is still connected
and the display cleanup would be taken care during the actual MST hub
disconnect. Also, handling the disconnect immediately on port status
notification leaves the usermode in an invalid state where it assumes
the display is still enabled and results in commit errors.
Change-Id: Ia9a58fadd89bd05746da25f142b54b31e8567258
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently previous mode information is passed to CP check phase
instead of the new incoming mode, which cause RC to silently
pass the check phase when there is a resolution mismatch between
the RC mask and new mode.
This change also adds various event log to better track RC codeflow.
Change-Id: I8953fd76e2cb0eb12e2df23038a7866edd3dcb1e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Enable the clks/irqs & update RSC state during encoder disable.
This ensures RSC is in correct state during the non-primary disable
commit as it might have entered idle power collapse before the
disable.
Change-Id: Idf82efb3a7bc895e1a97c6cdeeb62970184c8e5d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When a display is powered off, the DP driver currently clears the aux
state and forces it to OFF, expecting a subsequent hpd_low. But in MST
scenarios it is possible for individual displays to be unplugged and then
plugged back in without disconnecting the hub. In this use case, after
the unplug of last display, the aux state is in OFF, and on the
subsequent plug-in, the driver appends the ON flag, leaving both flags
to be set which is an incorrect state. This change removes this
assumption and properly sets the ON/OFF state on enable/disable
respectively.
Change-Id: I96355938a14c77fe958b86bd5f1dabad67584e4e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Scaler offset is missed while writing de lpf register,
which may cause DE works mainly on the left part of panel.
this change adds the offset to fix this issue.
Change-Id: I7cdc3afd3523cb9e15a7ae79adae07e2b52b8c2e
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
Allow TPG patterns to be displayed on command mode and
video mode panels.
Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Use pointer and allocate dynamic memory for msm_mode_info
in _sde_crtc_check_rois instead of object to reduce the
stack memory size.
Change-Id: Ida8fc7e2b94e19b3c791dcda55a465a4107ef976
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL.
Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Reset the wb crop configs from hardware, while disabling
concurrent writeback. This avoids stale configs which
affects the subsequent writeback session.
Change-Id: I4927effd0650bcdca2852a5d72c3e5478683a90f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Change moves destroying dp audio workqueue outside dp session_lock.
As part of disconnect, USB driver uses atomic notifier which holds
rcu_read_lock and calls into DP disconnect callback which needs
session_lock. If another DP threads holds DP session_lock then
we block RCU operations.
Change-Id: I5d565ca149a3a34ebd5ede4fb662982d87454f16
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change disables hw-fencing for the last commit before
vm transition. This avoids configuration issues if hw-fencing is
disabled in the incoming VM.
Change-Id: I573b7d1665f8cef442168bd0ab83a4b2b6cebbb6
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
During mode validation, DSC book-keeping logic is executed irrespective
of the panel DSC status. If the DSC blocks are available then the
corresponding mode is also set as DSC capable. This step is uncalled for
in a non-DSC panel scenario and might lead to unexpected behavior. This
change checks for panel DSC status before updating DSC book-keeping and
capability for the mode.
Change-Id: I30d6a4d7f3e772b7b13fcca6e318e96372a8becb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
