PCI bus resuming should be treated as fail once MHI
resume fails, to avoid the following operations those
depend on the result.
Change-Id: If3d21abf95cc2816bf6c34cb950ff430eee022d3
CRs-Fixed: 3795957
For dual chip solution, first chip may fail to probe because of pcie
driver is not ready. During second chip probing, first chip may retry
to probe. So, second chip may set/get plat_env[0], first chip may
set/get plat_env[1].
If sencond chip not attached, plat_env[0] will be cleaned. When
cnss_pci_probe() is called by first chip, cnss_get_plat_priv_by_rc_num()
will call plat_env[0]. However it is already NULL.
Change-Id: Ib959b1a524bf777fc6a826b2771611cb28b8cb99
CRs-Fixed: 3778085
Add wrapper __cnss_get_mhi_soc_info() to get SoC info
before registering MHI controller.
It calls mhi_get_soc_info() if downstream MHI bus driver
is enabled(CONFIG_MHI_BUS_MISC is enabled), while reads
register for SoC hardware version directly if not.
Change-Id: I97e53bf0a7e28b2b1027d8de5eaf9fc82bcd5cee
CRs-Fixed: 3712133
This reverts commit I55d554c4dc7d01ed82fffe79f666b340b1004765.
Default RC speed should be restored, shouldn't be restored to Gen2.
Change-Id: I23369aea1391c9e20c7aabe10506a7c9c37a4ba7
CRs-Fixed: 3702776
Fix potential NULL pointer dereference for tme_lite_mem
and tme_opt_file_mem, which are captured by static
analysis tool.
Change-Id: Ib2540669c55e771598dd21d8c2ae3eb297ffa67f
CRs-Fixed: 3716873
DRV last connected flag is cleared based on return from
host driver runtime_resume callback. In host triggered
SSR case runtime_resume callback return success without
actually resuming the bus and clearing DRV last connected
flag. When CNSS driver actually tries to resume the bus,
based on DRV last connected flag it calls MHI resume instead
of MHI DRV resume and fail to resume the bus. Bus resume
failure results in MHI driver go to bad state and fail to
trigger RDDM in device using SYS_ERR.
Fix this issue by clearing DRV last connected flag only after
bus resume is success.
Change-Id: Ia904f6965c2a2cbe0a483cf02ced91a09775ca62
CRs-Fixed: 3720847
For the cases where SOL is not enabled, Host REQ
reset will be used for second RDDM entry. If Host
REQ reset is success, start RDDM timer to wait for
RDDM status callback from MHI. If RDDM timer get
timedout read EE register to check for RDDM state
and schedule recovery.
Change-Id: I34253526ff4b20aedf8ab8f1f49831f68a3e0a35
CRs-Fixed: 3727389
This reverts Change-Id I848309440fdffd6517463e18190c03c1b7ed9269.
Reason for revert: Separate FW Binary not required
Change-Id: Ib694d38922f81895ce6bc01f4e38f95813625730
CRs-Fixed: 3726340
Fix misfiring of DEV SOL interrupt during enable_irq().
Ignore DEV SOL interrupt in case of device power off
as it is expected as part of off sequence.
In case of HOST triggered recovery, CNSS driver
tries to put device to RDDM first using MHI_SYS_ERR
and HOST_RESET_REQUEST if MHI_SYS_ERR fails. With
SOL enable, replace HOST_RESET_REQUEST with HOST_SOL.
Change-Id: I90c1a2dbd68c4c9c2e56d87dd1304a6ab0db53eb
CRs-Fixed: 3590408
As DIAG is now deprecated on Peach chipset onwards, create a new
MHI config struct that removes DIAG related channel configuration.
Then, register this new struct for peach chipset onwards.
Change-Id: I1ba1cadaa0d1a022d6c9af6d8ff14942d4f219cf
CRs-Fixed: 3684700
Send QMI message with SEC, RPR and DPR file information to WLAN FW, to
download TME binaries (sec, rpr, dpr files)
Change-Id: I0a4ab7ab127d493ef62d14658be2aa08b7d41606
CRs-Fixed: 3684131
Update TME-L patch name as per the target version 1.0 and change the
patch file location.
Change-Id: I1e5e8e6ac330a093f61e34029f8aec35fd3f26aa
CRs-Fixed: 3687807
Add PBL error logging on host console and dump SOC reset cause
register and PCIE_PCIE_BHIE_DEBUG_n register
Change-Id: I80ae44354b1efc05ed72f69a7e3ee8d358d840d7
CRs-Fixed: 3661767
CNSS2 registers PCI event callback for wake irq from
PCI driver. When callback is called CNSS2 completes
wake_event to notify the waiting threads. Currently,
initialization of wake_event completion is done after
PCI event callback registration causing issue when
PCI even callback for wake irq is called before wake_event
completion could initialize.
Initialize wake_event completion before PCIe event callback
registration.
Change-Id: If8c6ca5a5d5de5fc903b479d6d32ac0e5349f069
CRs-Fixed: 3648865
Currently Host driver calls cnss_force_collect_rddm API
to trigger RDDM and wait for dump collection. If device
fails to move to RDDM, CNSS driver initiate DEFAULT recovery
(which is recovery without RDDM dump collection) and return
failure to Host driver. Host driver sees error and again try
recovery which results in double recovery.
To avoid this issue, return success to Host driver if
CNSS driver has already initiated the DEFAULT recovery
and release rddm_complete wait event for DEFAULT recovery
cases also.
Change-Id: Ib4b324704d15b40ec98985745b1981522b3b4f2d
CRs-Fixed: 3627928
Remove unwanted delay from PCIe link down recovery sequence
1. Wait for wake event from PCIe driver instead of hardcoded wait.
2. After link recovers, wait for device to move to RDDM mode
instead of starting rddm timer.
3. If device fails to move to RDDM, assert HOST SOL and initiate
side band recovery.
Change-Id: I5a4096ac781dd8f5011b07b0ffb669815a968570
CRs-Fixed: 3590419
Race condition seen between WAKE interrupt handler
and HOST triggered recovery. Due to the race PCI
link up is called back to back. Protect PCI bus
resume with bus_lock mutex.
Change-Id: Ifc140921bdf803bc2d46365b4e5a59cba34ee715
CRs-Fixed: 3614970
Current code has compilation errors
when compiling for sun. sched_clock()
was moved to clock.h, and iommu_map API
was changed with new sun kernel. Fix
this by updating code for new kernel
apis.
Change-Id: I77029fcc74142f3f650dc289c8d19c121eba6445
CRs-Fixed: 3603129
There is known pcie linkdown issue for qca6490 if gen3 speed is used.
Previous solution is to downgrade to gen2 before enumeration, but it
doesn't work if platform support multiple wlan chips where device id
can't be determined until enumeration success.
The fix is:
1, Enumerate all devices with gen1 speed
2, When enumeration done, restore to gen2 if device is qca6490
Change-Id: I55d554c4dc7d01ed82fffe79f666b340b1004765
CRs-Fixed: 3612384
When PCIE linkdown happen, IRQ handler will disable IRQ line then
trigger SSR. disable_irq() is used but it introduce sleep in IRQ
context(unexpected). Crash will happen if CONFIG_SCHED_WALT is set:
android_rvh_schedule_bug+0x4/0x8
__might_sleep+0x50/0x84
synchronize_irq+0x48/0xc4
disable_irq+0x70/0x9c
cnss_pci_handle_linkdown+0x1a8/0x1c0 [cnss2]
cnss_pci_event_cb+0x148/0x348 [cnss2]
msm_pcie_notify_client+0x110/0x180
msm_pcie_handle_linkdown+0x2d8/0x2f8
handle_global_irq+0x464/0x5dc
To avoid this issue, should use disable_irq_nosync(), which doesn't
wait IRQ handler to finish. It should introduce no side effect, as
the whole device will be restated later by SSR.
Change-Id: I5ec96d41337a14280333ab9fea0c1f6132a532af
CRs-Fixed: 3548604
Move trivial repetitive logs from cnss IPC logs to
cnss-long IPC logs. This will reduce the chances of
losing important logs required for debug.
Change-Id: I9cfe76614603d5fb9b3e5d4a2f062abbb7fa754f
CRs-Fixed: 3580107
In current implementation, the error log not record the
return value of setting pci power function, with this return
value we can know the reason of why setting pci power failed.
Change-Id: Icf1fdba16faf539334704ca1f8ce24fecd49aa94
When feature CNSS2_CONDITIONAL_POWEROFF enabled, wlan chip HST and
HSP will not power off in cnss probe. PCI link will not be triggered
to retrain once CNSS2_ENUM_WITH_LOW_SPEED enabled.
So, add API cnss_pci_link_retrain_trigger() to trigger pci link retrain
when HST and HSP not power off.
Change-Id: I2ba44837a03b09b1ef3cd0c23a780b89ff837740
CRs-Fixed: 3491396
Complete power_up event on probe failure to avoid timeout while
waiting for this event during unregister of host driver.
Change-Id: Ie262305ef960ab40cd38b4a695d409eb36fcf0d7
CRs-Fixed: 3565756
PCI link info contains maximum link speed and link width
supported by platform. WLAN FW will use supported link
speed to restrict link speed switch upto maximum
supported speed.
Change-Id: Icdf54c8729192faf4966514b57bd826f86652065
CRs-Fixed: 3535790
In some scenarios, during force FW assert,
cnss_pci_pm_runtime_get_sync might not resume bus.
Make sure PCI bus is resume before accessing.
Change-Id: Ic5c17c3385318dbc739358ac7ccdb148aed1052a
CRs-Fixed: 3540601
With VT-d disabled on x86 platform, only one pci irq vector is allocated.
Due to the irq is not freed when suspend, the kernel will migrate irq to
CPU0 if it was affine to other CPU and then allocate a new MSI vector,
which cause the issue about no irq handler for vector once resume since
the driver only configure MSI data once during driver loading.
The fix is to set irq vector affinity to CPU0 before calling request_irq
to avoid the irq migration.
Change-Id: Id366e33113089f50899eb3631db66dcde0999d84
CRs-Fixed: 3550165
Send QMI message with TME-L patch information to WLAN FW, to
download TME-L patch.
Change-Id: Ieae07c0f761ada45ffcb990b1412654b9c6862b1
CRs-Fixed: 3521187
Host triggered force assert can be called asynchronous.
As part of force assert, CNSS dumps few MHI registers and
trigger RDDM asynchronously. There are chances of race between
force assert and runtime suspend.
To fix that take runtime get reference before MHI operations and
runtime put later.
Change-Id: Icef23910587ff280270bdd7c60ad8eba392822e9
CRs-Fixed: 3464127
Some platform PCIe RC impedance can't achieve the target defined in spec.
It will result to Genoa card link down. To WA the issue, downgrade RC speed
to Gen1 for auto Genoa EP. Because the linkdown issue may happen during
enum, and before enumunation we do not know EP device ID, so set init
speed to Gen1, and then restore speed to default for others wifi chip.
The change does not affect Genoa throughput, because Gen1 speed is enough
for Genoa.
Change-Id: Iffdbf8b98a82c200faf11edcdd180213366ed6ca
CRs-Fixed: 3479848
Add support for AUX UC download functionality if aux support is
indicated by both host and fw.
Change-Id: I3bfbebbb5cdfbbaa350a34378ab2f0809f27affb
CRs-Fixed: 3402104
MHI INIT called during host driver registration leads to MHI state
mismatch because MHI is already in INIT state due to power up of
device as part of ongoing self recovery.
To fix this issue, avoid powering up device during recovery if host
driver is not registered. Device would be powered up later during
host driver registration.
Change-Id: I534dfc0e389ba97a6e2c4869d42be5ecff9609b3
CRs-Fixed: 3476947
Read MSI-X address from device tree file and initialize
MSI-X address and data to support MSI-X interrupts.
Change-Id: I7cc43ca4d3e4c937f09facf12dd02437ddc2e039
CRs-Fixed: 3488821
API cnss_send_buffer_to_afcmem pass AFC data from driver to target
which is not changed in platform driver, and it is pass-through byte
stream for platform driver.
Change the AFC data pointer in API from char* to const uint8_t*.
Change-Id: Ib492dbcf028776858926d8a3e11edc528566fac1
CRs-Fixed: 3478093
Cnss2 driver receives cnss_pci_smmu_fault_handler cb from smmu
driver whenever wlan fw access illegal IOVA address. In
cnss smmmu fault cb handler, cnss2 driver rings trace stop
door bell register to stop tracing in wlan fw. This will
help to get proper traces to debug where illegal access
is happening in wlan fw.
Change-Id: I953ced55d4d847ccaabad15f5f70150aec8aabd6
CRs-Fixed: 3459443
Add one new device tree config item "qcom,sleep-clk-supported"
to support enable 32k internal sleep clock in case it has no
external 32k clk attached in wlan chipset HW. Like qca6390
on some auto platform, host need explicitly tell firmware
to use internal sleep clock, otherwise it will cause LMAC
ps failure.
Change-Id: I52f5d332a912235596eb127ab8e4660355988038
CRs-Fixed: 3448595
Add new "qcom,no-bwscale" under child device node to
indicate it want to disable bw scalling.
And the background is like HSP, it has stability issue
with some specific pcie cable with gen3, so it will
negotiate with RC side to change from gen3 to gen2
with MHI_ER_BW_SCALE_ELEMENT_TYPE event, which will
impact all the platform that want to keep use gen3.
So add this device tree config item to skip the link
speed negotiation.
Change-Id: I4a8d94a50dd740b84c3eeac435c5a19098b79ad9
CRs-Fixed: 3435289
Access to PBL and SBL log region in SRAM is restricted in
Mission mode. Avoid PBL/SBL log region dump in Mission mode.
Change-Id: Ia8813ccd9e2c0339c280e6cb6d6f0bab0bee206e
CRs-Fixed: 3432159
It costs 4M when loading cnss2, if device id is QCA6490 and enabled
CONFIG_CNSS2_DEBUG. Which is big memory consumption for low rate issue
debugging. So add CONFIG_DISABLE_CNSS_SRAM_DUMP to disable sram_dump.
Change-Id: Iacf338a3cc8f1583e16034a9873029a450fd254a
CRs-Fixed: 3441274
Currently genoa is using lower 32 bits of 64 bit dma
bitmask. Unexpected access of higher 32 bits may cause
issues.This code change avoids such possibilities.
Change-Id: I8bf17056a12661a7c50333bf5897721d363550a3
CRs-Fixed: 3428036
At the auto platform, DRV feature is not applicable.
So do not issue any DRV related operation from cnss2
side, which may cause the RC PHY not ready in the LPM
case.
Change-Id: Iefae9a885c1adc289da518d65a2974e127bdf359
CRs-Fixed: 3419811
