Define the generic R8A7794 part of the sound device node.
This sound device is a complex one and comprises the Audio Clock Generator
(ADG), Sampling Rate Converter Unit (SCU), Serial Sound Interface [Unit]
(SSI[U]), and Audio DMAC-Peripheral-Peripheral.
It is up to the board file to enable the device.
This patch is based on the R8A7791 sound work by Kuninori Morimoto.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the external audio clocks (signals AUDIO_CLK[ABC]) required by
the sound driver. Boards that provide audio clocks need to override the
clock frequencies.
This patch is based on the commit 0d3dbde84a ("ARM: shmobile: r8a7791:
add audio clock on DTSI").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LCDK is the successor to the late Hawkboard.
Among the differences are the flash (16bits vs 8bits) and some pins
(MMC, LEDs, buttons, some external connectors), however the main
components remain the same (eth. phy, audio codec, video decoder and
DAC) except for the main PMIC, different and hard-wired on the LCDK (the
LDOs and DCDCs are always on).
A DT-only boot with this addition gives functional UART, reboot via
watchdog, RTC, ethernet and MMC (I added the CD GPIO for the MMC
although davinci_mmc doesn't call the OF facilities of mmc core).
Cc: Sekhar Nori <nsekhar@ti.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds 2 pinctrl groups (rtscts, rxtx) for each of the 3 UARTs.
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
For some devices, the PWMSS is a parent of eCAP and ePWM and provides
the functional clocks for those submodules. The ti,am33xx-ecap and
ti,am33xx-ehrpwm bindings were based on this parent child relationship
where the functional clock would be grabbed from the module's parent.
However, DA850 doesn't have a PWMSS and the eCAP and ePWM provides
their functional clock themselves. Therefore, prefer the new binding
that doesn't assume this parent child relationship.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
[nsekhar@ti.com: minor commit message fixes]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
imx6ul-pico-hobbit has a bcm4343 wifi chip connected to usdhc2 port.
Add support for it.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The SoC internal regulators for the CPU and the SoC come from the
DA9063 vdd_core and vdd_soc. Add this relationship to the device tree
so that the voltage drop on the SoC internal LDO regulators can be
minimized.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Several dts files set a bit in the SPEED field for pads
RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there
doesn't have an effect and the bit reads as zero.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Create a new device tree file for the Broadcom Northstar Plus
bcm958622hr SVK. This SVK has 2GB RAM, 5 port Ethernet, 2 PCI slots,
and 1 UART. Also, it has the ability to reboot via GPIO. To be added
in the future are support for the USB and SLIC audio.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Create a new device tree file for the Broadcom Northstar Plus
bcm958623hr SVK. This SVK has 2GB RAM, 5 ports Ethernet, SATA, 2 PCI
slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be
added in the future are support for the USB and SLIC audio.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Create a new device tree file for the Broadcom Northstar Plus
bcm988312hr SVK. This SVK has 2GB RAM, 5 ports Ethernet, 2 eSATA, 2 PCI
slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be
added in the future is support for the USB.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Create a new device tree file for the Broadcom Northstar Plus
bcm958522er SVK. This SVK has 2GB RAM, 2 ports Ethernet, 2 PCI slots,
and 1 UART. Also, it has the ability to reboot via GPIO. To be added
in the future is support for the USB.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Create a new device tree file for the Broadcom Northstar Plus
bcm958525er SVK. This SVK has 2GB RAM, 2 ports Ethernet, 2 eSATA, 2 PCI
slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be
added in the future is support for the USB.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the ability to reboot the bcm958625xmc board via GPIO.
Unfortunately, not all of the NSP based boards use the same GPIO pin
and one doesn't have the ability to reboot via GPIO at all. So, this
will need to be specified per DTS file.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the ability to reboot the bcm958625hr board via GPIO.
Unfortunately, not all of the NSP based boards use the same GPIO pin and
one doesn't have the ability to reboot via GPIO at all. So, this will
need to be specified per DTS file.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The BCM958625HR board has 2GB of RAM available. Increase the amount
from 512MB to 2GB and add the device type to the memory entry.
Fixes: 9a4865d42f ("ARM: dts: NSP: Specify RAM amount for BCM958625HR board")
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add PWM support to the device tree for the Broadcom Northstar Plus SoC.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Driver for Northstar USB 2.0 PHY was added in 4.7-rc1 by:
commit d3feb40673 ("phy: bcm-ns-usb2: new driver for USB 2.0 PHY on
Northstar").
It should be used to let EHCI platform driver init PHY.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the layout of the switch ports found on the BCM958625HR reference
board. The CPU port is hooked up to the AMAC0 Ethernet controlelr
adapter, so we also enable it.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the Switch Register Access Block node, this peripheral is identical
to the BCM5301x Northstar SoC, but we utilize the SoC-wide
"brcm,nsp-srab" compatible string to illustrate the integration
difference here.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add Device Tree entries for the Ethernet devices (AMAC) present on the Broadcom
Northstar Plus SoCs.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This will allow u-boot to fill in a mac-address for Orange Pi 2
variants which use an sdio wifi without an eeprom for the mac.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
There is a new Orange Pi PC *Plus* version available now,
this is an extended version of the regular Orange Pi PC
with sdio wifi and an eMMC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[Maxime: Fix model and compatible]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we've all the necessary bits in place we can enable
full otg support on these tablets.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC
family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Commit 1140011ee9 ("mmc: sdhci-pxav3: Modify clock settings
for the SDR50 and DDR50 modes") has extended the Device Tree
binding used to describe PXAv3 SDHCI controllers in order to be
able to use the SDR50 and DDR50 modes.
This commit updates the Device Tree description of the Armada
39x SDHCI controller in other to take advantage of this
functionality.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
