The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
But these boards don't have a memory node defined, so removing the
skeleton.dtsi inclusion from omap3.dtsi will cause a change in the
compiled DTB. Add a dummy memory node so the compiled DTB doesn't
change if the skeleton.dtsi is removed from omap3.dtsi.
Eventually the correct starting addresses and sizes should be used
but I didn't find that information.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
But the sl50 board doesn't have a, so removing the skeleton.dtsi
inclusion from am33xx.dtsi will cause a change in the compiled DTB.
The board has 512 MiB of RAM and its starting address is 0x80000000,
so add a proper memory device node in the DTS.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Current clocks tree definition for CPSW/CPTS doesn't
correspond TRM for dra7/am57 SoCs.
CPTS: has to be sourced from gmac_rft_clk_mux clock
CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 ->
-> GMAC_MAIN_CLK (125 MHZ)
Hence, correct clock tree for GMAC_MAIN_CLK and use proper
clock for CPTS. This also require updating of CPTS clock
multiplier.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit fixes the clock data inside the DRA7xx clocks device tree
structure for the gmac_gmii_ref_clk_div clock. This clock is actually
the GMAC_MAIN_CLK and has nothing to do with the register at address
0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
set to 1 in order to use the GMAC_RMII_CLK instead of the
GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
resolved and the clock tree is fixed up.
Additionally, a new clock called rmii_50mhz_clk_mux is defined that
does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
source clock for the RMII_50MHZ_CLK.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com>
Reviewed-by: Trenton Andres <trenton.andres@garmin.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Integrator/CP CLCD VGA display can now be registered
fully from the device tree. Delete the board file code and
add the display definition to the DTS.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the clocks on the core module to the Integrator/AP
board: a 24MHz chrystal, and two special-purpose ICST525
dividers, one used to clock the CPU core and another auxilary
oscillator.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The two clocks present on the Integrator/AP baseboard and
accessible through its system controller is the PCIv3 bridge
clock and the PCI bus clock. Define the proper device tree
nodes for these.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The UniPhier reset controller driver has been merged. Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since DRA7 has multiple PCIe Rootcomplex, add "linux,pci-domain"
property to assign a PCI domain number to each of the host
bridges.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM335x ICE board has a rotary-switch connected to PCA9536 I2C GPIO
expander. The position of the rotary-switch is reflected by status of
GPIO lines. Add gpio-decoder node to read these GPIO line status via
gpio-decoder driver and report it as an input event to the system.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
All UniPhier device trees have the common prefix "uniphier-", so
"ph1-" is just making names longer. Recent documents and other
projects are not using PH1- prefixes any more.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Colibri modules need to be powered using the power pins 3V3 and
AVDD_AUDIO. Add fixed regulators which represent this power rails.
Potentially, those power rails could be switched on a carrier
board. A carrier board device tree could add a own regulator with
a GPIO, and reference that regulator in a vin-supply property of
those new module level system regulators. This also synchronize
the name of the +3.3V regulator with the one used in the Colibri
VF50/VF61 device tree.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Move SD-card definition to module level. While at it, also disable
write-protect since the Colibri standard does not define a pin for
SD-Card write-protection.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix misspelled "ti,x-plate-ohms" property name of TI TSC2046
touchscreen controller.
Fixes: d09e6beafa ("ARM: dts: imx7d-sdb: Add support for touchscreen")
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The SPI controller in the arch/arm/boot/dts/armada-39x.dtsi file has moved
to a different location in the hierarchy, which breaks the overrides
in the board specific file:
Warning (reg_format): "reg" property in /soc/internal-regs/spi@10680/spi-flash@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/internal-regs/spi@10680/spi-flash@1
This changes the board to reference the spi controller by its label
(which has not changed) rather than the full path.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 0160a4b689 ("ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node")
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
imx6ul-pico has WDOG1_B pin connected to the PMIC.
Pass the 'fsl,ext-reset-output' property so that the watchdog
can trigger a system POR reset via PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
At power on, pca953x GPIO pins are configured as input and may cause
unexpected interrupts. Configure the unused pins as GPO low to
avoid unexpected interrupts.
Signed-off-by: Ken Lin <ken.lin@advantech.com.tw>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Configure the DWMAC FIFO sizes, burst length and threshold DMA mode on
LPC18xx/43xx SoCs. These parameters are needed for correct operation of
the Ethernet MAC. The DWMAC on LPC18xx/43xx does not support RSF DMA
mode and therefore must use threshold mode.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
The 'compatible = "nxp,jc42"' binding only happened to work because
the Linux driver is named jc42. The driver now supports generic
bindings for JC-42 compatible chips, so use the generic binding instead.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
The inet-d978_rev2 is a pcb used in generic A33 based tablets. It features
volume buttons, micro-usb otg, headphone connector and a power button.
On the board a Realtek RTL8723BS SDIO Wi-Fi module are soldered, and there
is also a accompanied board which has a Goodix GT9271 soldered.
As this board is desired to create tablets with a Home key dealed by
GT9271, a LED is present at the front panel at the position of the
Home key.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R_PIO device node is missing #interrupt-cells, which causes
interrupt parsing to fail to match it as a valid interrupt controller.
Add #interrupt-cells to it. Also remove the unnecesary #address-cells
and #size-cells.
Fixes: 1ac56a6da9 ("ARM: dts: sun9i: Add A80 R_PIO pin controller device
node")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Rename the reference-design-tablet touchscreen node from gsl1680 to
touchscreen, all? tablets seem to use the same power and interrupt
gpio-s, but not all tablets use a gsl1680 controller making the
gsl1680 name somewhat misleading.
Also move the reg and compatible property to the actual tablet dts
as they may differ per tablet.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add a dts file for the Empire Electronix M712 tablet, this is a 7" A13
tablet, with micro-usb (otg), headphone and micro-sd slots on the
outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV
wifi chip and a DMART06 (1238a4) accelerometer.
Note currently the dts for this is somewhat empty. This will change
once we add support for the touchscreen and accelerometer.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ehci1/ohci1 pair on the ba10-tv-box is connected to an USB-2 wifi
module soldered on the PCB, so there enabling ohci1 is not necessary.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Silicon limitation i845 documents how to cope with false
disconnection condition on USB2 PHY. Reference: AM572x
silicon errata document SPRZ429H, revised January 2016.
Using compatible "ti,dra7x-usb2" enables the recommended
software workaround for this issue. Use it for USB1 PHY.
The workaround is already in place for USB2 PHY.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The wega board has a TLV320AIC3007 connected via McASP0. In the default
configuration, no external crystal is mounted. We run a system clock of
25 MHz, so we use the audio codec PLL for audio clock generation.
Signed-off-by: Stefan Müller-Klieser <s.mueller-klieser@phytec.de>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM572x IDK has a Spansion s25fl256s1 QSPI flash on the EVM connected to
TI QSPI IP over CS0. Hence, add QSPI and flash slave DT nodes.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
According to AM572x DM SPRS953A, QSPI maximum bus speed can be 76.8MHz.
Therefore, increase the spi-max-frequency value of QSPI node to 76.8MHz
for DRA74 and DRA72 evm. This improves flash raw read speed by ~2MB/s.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the device tree parsing using the regulator framework
there is a no longer a need for separate compatibles for
individual regulator nodes. Hence removing them all.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the device tree parsing using the regulator framework
there is a no longer a need for separate compatibles for
individual regulator nodes. Hence removing them all.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the device tree parsing using the regulator framework
there is a no longer a need for separate compatibles for
individual regulator nodes. Hence removing them all.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the device tree parsing using the regulator framework
there is a no longer a need for separate compatibles for
individual regulator nodes. Hence removing them all.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Without this, the memory will remain active during poweroff consuming
extra power. Please note revision 2.1 PMIC seems to fail when DCDC3
disable is attempted, so this is not done on that PMIC revision. The
PMIC revision checks in the regulator patches make sure of this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Without this, the memory will remain active during poweroff consuming
extra power.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dcdc3, dcdc5, dcdc6 supply ddr and rtc respectively. These
are required to be on during suspend. Hence set the state accordingly.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
