Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Increase the maximum number of mixers per crtc to 4 to
support 4LM use case. This change also increases the number
of data path to 4 to support 4LM in continuous splash handoff.
Change-Id: I4655017dcb405fad69513bebb8fd7f848fc5873d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.
This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.
Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This reverts commit a4c2827a47.
The change is not needed on 5.4 since BW limits have moved to
user-space per-target based XML file, and there are already other
properties for specifying the various linewidth parameters.
Change-Id: I87d81047678869bba6f8ec98104dec17c7a9ace2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add scaling linewidth variable and logic changes to get
valid max linewidth values for inline rotation and scaling.
Modify linewidth check to compare with scaler source width.
Change-Id: I7c63175e568ecb524f9cdf8ada1d7c6fdc999236
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
Update the VDC-m hardware version in the display driver as per
the latest programming guidelines.
Change-Id: I0073cb7b713599de43f2a675202390df3b4a1d58
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Based on the hardware catalog if dpu supports demura, driver will
install the drm properties specific to the feature. Change added support
for creating demura properties and exposing via drm frame-work.
Change-Id: I58f5b12ca660d826e6e0b7e1f212bdf3c5e41905
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
If DPU hardware supports demura feature, install the connector
properties related to demura feature.
Change-Id: Ieaddfc695e9f57e3c45e2bc0bd2c2e103f895ba8
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.
Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Separate the horizontal and vertical max downscale checks
as pre-downscale introduced different limits on different
axes. Also cleanup the variable names for max downscale
limit when pre-downscale is not enabled.
Change-Id: If01aac1844d0bd5133502a50dbc38197e11da5d5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change parses SPR hw block entries from device tree and populate
SPR block as sub block of DSPP block. Change also enables register dump
by registering sub blocks with sde driver register dump routine.
Change-Id: Ic603cd3cc001dddce5dfea61341c166a5fec1682
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds logic to align timing engine vsync with panel
tear check if it is supported.
Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Register the MDSS_HW block (at base offset 0) for access via the
sde_reg node in SDE's debugfs directory. This is needed for
validating correct UBWC register programming.
Change-Id: I2494e066a7603747f2ec12546e58a17f2120a521
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Support different safe, danger and creq qos lut
configuration based on display fps. It also removes
the fill level calculations from sspp and wb block
because mdss hw supports simple configuration.
Change-Id: I203e4300c9eab27d3632c890bedd6383cca0e5a8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add support for hardware based rounded corner part of
color processing framework.
Change-Id: I3e5f4dac6ffc759bb940215b7621ac716f255169
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change updates the block offsets for concurrent writeback
blocks and fixes the register dumping logic.
Change-Id: I41b540773fea60e66cab5d476dff1a19b4f4b3db
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change programs dither based on user mode input data and
reprograms the dither when device comes out of power collapse.
Change-Id: I83be20c8eb2dc2221cc57cd2395f6512338ff6ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
A new LUTDMA HW instance has been added to support programming of
SB features via LUTDMA. This change adds corresponding support for
the new SB LUTDMA, including catalog parsing, reg_dma init/deinit/ops
updates and new opcode support.
Change-Id: I0fed7a6e93cd96fe9fe562d2470a8789b161d1bc
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Extend unified flush bit support to control new DSPP
SB LUTDMA bit.
Change-Id: Iba941a4bcd140ceb88e49ab83700c4baef804e0f
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add hardware catalog support for VDC-m block to parse
the register offsets and feature capabilities.
Change-Id: I1bfbc4b6e7e9f34738d49fecdef4b427a0ccded7
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change adds the hooks to enable the active signal override
in power collapse sequence. Active signal override is needed to
disable the clock gating when the power collapse sequence
is running.
Change-Id: I9edaed7960b236b3d0179cb67f9cc2c9b3546c9d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change adds additional dsc hw sub-blks and their
advertized capabilities. These are required for supporting dsi 1.2 hw
and making the code backward compatible with older hw version.
Change-Id: I84d86ad4f6ac2dd76324bbfd5600b010738b3310
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Add support for HDR memory pool blocks aligned to a 4k page
address. This feature must be enabled by setting the
corresponding feature bit for supported targets.
Change-Id: I696ffb6ce3b607741f26496d40e2296c4c5bdb4b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
SDE HW from lahaina has moved the DSPP flush bits from CTL_FLUSH
to new CTL_DSPP_x_FLUSH registers. This change brings in
support for programming the new DSPP flush registers which
allow more fine-grained control over what sub-blocks within
each DSPP get flushed.
Change-Id: Ie16c9b153d607bd7627ba02480813ab588bbe2ea
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
De-couple the horizontal and vertical pre-downscale checks since
this block can be used in cases where only X-axis downscaling
is needed.
Change-Id: I2e7d30863baed98e9f7fa0a328837691f0bc75a5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Determine inline rotation capabilities and parameter values
from the inline rotator revision. This reduces the number of
capabilities required to be added for each new target.
Change-Id: I3ae02938d51be5a5419b50303c1f244be12b8c47
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Don't expose the prefill requirements for inline rotation.
These values are not used within the driver, so move these
settings to user-space.
Change-Id: Ie1038c5804047fafe0ee3129b993d83d4d31b386
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add support for enabling pre-downscale block to increase the
maximum downscale capability for true inline rotation use cases.
Change-Id: Ifa544bb0ae69439abef4bd427134290090fe7230
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Advertise the new formats supported with true inline rotation v2 HW
(ABGR8888 compressed and P010).
Change-Id: I0a1b6dfd6bcfd82d9bc61e87680d2c584615e113
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
* changes:
disp: msm: sde: use device tree node to enable INTF TE capability
disp: msm: sde: refactor sde_hw_interrupts to use offsets from catalog
disp: msm: sde: get INTF TEAR IRQ offsets from device tree
disp: msm: sde: rename MDSS_INTR_* enums to SDE_INTR_*
disp: msm: sde: add Lahaina version checks
disp: msm: sde: move all hw version checks in to the catalog
Migrate to icb framework API in drm and sde driver. And
also removes old msm_bus custom APIs from the driver.
Change-Id: Ifcf6d6f157594638075742fe328b29a9be065bca
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Set the INTF TE capability bit only on interfaces which have a non-zero
value in the device tree node qcom,sde-intf-tear-irq-off instead of
enabling it for all interfaces based only on the HW version. The HW
doesn't support TE programming for non-TE enabled interfaces, so this
patch only populates the TE ops for those which support it.
Change-Id: I00518e846dc44e1e0808a049625dc14099656e11
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Refactor the SDE interrupts module to use the offsets in the catalog.
This avoids hard-coding offsets for interrupts within a block's
address space so when that block's base address is relocated the
interrupts for that block are shifted as well.
Change-Id: I08f66c0e93bbe102dfe67350c97c5c7a4fb5039a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The INTF TEAR IRQ block offsets can shift between targets. Therefore,
to allow dynamically setting these offsets they should be specified
in the sde device tree node qcom,sde-intf-tear-irq-off.
Change-Id: I2948bc6eaa31fe5e180379770d88e7be72b6d345
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
