Update codec clock sequence to clear Fs counter to avoid
unexpected behavior during bootup.
Change-Id: I78da6dadd26989cf1f39f71b941a209c2af4cef2
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Add ratelimit to supress the logs flooding at the
time of SSR.In all places defined ratelimit as,
in 1sec one debug msg prints.
Change-Id: I6dfe140848e5cecb1b311c432f8311cdf0615a58
Signed-off-by: Prasad Kumpatla <nkumpat@codeaurora.org>
During SSR/PDR use cases, core clock count in different
macros becomes stale and muxsel registers are accessed
leading to NOC errors. Update muxsel registers only after
clock counts are reset after SSR/PDR recovery.
Change-Id: I656f8e7ddc8a92a325c2ba644f1a945cbafb08a0
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Because of a HW limitation in DSP, while switching
RCG from TX MCLK to VA MCLK for SVA use cases
a glitch is seen on AHB bus leading to data
corruption in registers.
So, while doing a mux switch for VA RCG clock selection,
do not configure the muxsel register in HLOS as it is
taken care in DSP itself as a workaround for HW limitation.
Change-Id: Iccbe714397796259fa55f9852ece387e949b12e8
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
Synchronize the bolero fs gen sequence updates
in order to avoid race conditions.
Change-Id: Idb95dcf1d5f5f4d24ab507ccd221d399a6b5a021
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Vote for codec core and NPL clocks before regcache_sync
to avoid unclocked access of bolero registers.
Unvote once the regcache sync is done.
Change-Id: Iae45f487113c55318f33cd1950e2d6b64bcd945a
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Reset GFMUX reg for va-macro and wsa-macro when adsp is up
after SSR. And check if clock is enabled before accessing
register to avoid kernel panic.
Change-Id: Idce9695be552cab0e8e389cf72eeb7a67a754bf9
Signed-off-by: Meng Wang <mengw@codeaurora.org>
After SSR/PDR, the lpass clocks will be in off state. Force restart
clocks after SSR/PDR, if enabled before SSR/PDR, to reenable the clocks.
Change-Id: I3d850d92bdc6324aa7a64a83a9066f388a85c7f7
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Exposure of driver bind/unbind to userspace via sysfs may
lead to unexpected behavior.
Hide bind and unbind by driver attribute.
Change-Id: I20d6ee653bcc16af15d6368664aaf240c6645cd0
Signed-off-by: Xiaojun Sang <xsang@codeaurora.org>
When SSR happens, use dev_up flag in codec
to bail out from clock enablement routine.
During interrupt processing if clock enable fails during
SSR, exit isr routine without disabling clock.
Change-Id: Ie2b56521daa70790d6ef53a06c7becc2ee8010a4
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Add Bolero clock resource manager driver to handle/manage
bolero clocks for all the concurrency usecases like record
+ voice activation.
Change-Id: I970a05d96fc9060b44bfe670d465f0b9d72cc53b
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
