asoc: codecs: Do not update VA clk muxsel register

Because of a HW limitation in DSP, while switching
RCG from TX MCLK to VA MCLK for SVA use cases
a glitch is seen on AHB bus leading to data
corruption in registers.
So, while doing a mux switch for VA RCG clock selection,
do not configure the muxsel register in HLOS as it is
taken care in DSP itself as a workaround for HW limitation.

Change-Id: Iccbe714397796259fa55f9852ece387e949b12e8
Signed-off-by: Aditya Bavanari <[email protected]>
Signed-off-by: Vignesh Kulothungan <[email protected]>

asoc/codecs/bolero/bolero-clk-rsc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/of_platform.h>
@@ -247,10 +247,13 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
 
 	if (enable) {
 		if (priv->clk_cnt[clk_id] == 0) {
-			ret = bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
+			if (clk_id != VA_CORE_CLK) {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
+								default_clk_id,
 								true);
-			if (ret < 0)
-				goto done;
+				if (ret < 0)
+					goto done;
+			}
 
 			ret = clk_prepare_enable(priv->clk[clk_id]);
 			if (ret < 0) {
@@ -268,9 +271,19 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
 					goto err_npl_clk;
 				}
 			}
-			iowrite32(0x1, clk_muxsel);
-			bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
+
+			/*
+			 * Temp SW workaround to address a glitch issue of
+			 * VA GFMux instance responsible for switching from
+			 * TX MCLK to VA MCLK. This configuration would be taken
+			 * care in DSP itself
+			 */
+			if (clk_id != VA_CORE_CLK) {
+				iowrite32(0x1, clk_muxsel);
+				bolero_clk_rsc_mux0_clk_request(priv,
+							default_clk_id,
 							false);
+			}
 		}
 		priv->clk_cnt[clk_id]++;
 	} else {
@@ -282,20 +295,31 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
 		}
 		priv->clk_cnt[clk_id]--;
 		if (priv->clk_cnt[clk_id] == 0) {
-			ret = bolero_clk_rsc_mux0_clk_request(priv,
+			if (clk_id != VA_CORE_CLK) {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
 						default_clk_id, true);
 
-			if (!ret)
-				iowrite32(0x0, clk_muxsel);
-
+				if (!ret) {
+					/*
+					 * Temp SW workaround to address a glitch issue
+					 * of VA GFMux instance responsible for
+					 * switching from TX MCLK to VA MCLK.
+					 * This configuration would be taken
+					 * care in DSP itself.
+					 */
+					iowrite32(0x0, clk_muxsel);
+				}
+			}
 			if (priv->clk[clk_id + NPL_CLK_OFFSET])
 				clk_disable_unprepare(
 					priv->clk[clk_id + NPL_CLK_OFFSET]);
 			clk_disable_unprepare(priv->clk[clk_id]);
 
-			if (!ret)
-				bolero_clk_rsc_mux0_clk_request(priv,
+			if (clk_id != VA_CORE_CLK) {
+				if (!ret)
+					bolero_clk_rsc_mux0_clk_request(priv,
 						default_clk_id, false);
+			}
 		}
 	}
 	return ret;
@@ -304,7 +328,8 @@ err_npl_clk:
 	clk_disable_unprepare(priv->clk[clk_id]);
 
 err_clk:
-	bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
+	if (clk_id != VA_CORE_CLK)
+		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
 done:
 	return ret;
 }