Currently for REO reinject path, first fragment is in the
linear part of the skb buffer while other fragments are
appended to skb buffer as non-linear paged data. The other
point is that for REO reinject buffer, l3_header_padding is
not there, meaning ethernet header is right after struct
rx_pkt_tlvs.
Above implementation will have issues when WLAN IPA path is
enabled.
Firstly, IPA assumes data buffers are linear. Thus need to
linearize skb buffer before reinjecting into REO.
Secondly, when WLAN does IPA pipe connection, RX pkt offset
is hard-coded to RX_PKT_TLVS_LEN + L3_HEADER_PADDING. Thus
need to pad L3_HEADER_PADDING before ethernet header and
after struct rx_pkt_tlvs.
Change-Id: I36d41bc91d28c2580775a1d2e431e139ff02e19e
CRs-Fixed: 2469315
Update wlan_chan_to_freq and wlan_freq_to_chan utility functions to
handle invalid channel number and freq value of 0 respectively.
Change-Id: I92e2d5026bb93439b77b749d447654ceb9413fde
CRs-fixed: 2546771
During cleanup path in STA mode, remove false assert as there is just self
dp_peer with no TX and RX TIDS setup.
Change-Id: Id6be7a6b3823c41ddbff67926bda240a4e9b6bd0
CRs-Fixed: 2547680
Due to channel number ambiguity with introduction of 6Ghz support
policy manager APIs are updated to use frequency values instead
of channel number. Update set pcl WMI handling to adapt for frequency
usage.
Change-Id: I69bac781036ed9faee8842190d9bf19abca3ec61
CRs-fixed: 2540002
The decision to do CAC when a vap is coming up should be taken based on
the previous channel and current channel. Introduce previous channel
in DFS structure and update it when the current channel is updated.
Use the previous channel and current channel in DFS structure to
decide whether the CAC should be done or not when the vap is coming
up.
Change-Id: Ia359025d5029713c32696dacee5b89618a1c9707
CRs-Fixed: 2538653
During hal write register first device force wakeup
request is done. If force wakeup request fails register
write is not done and the execution continues. This leads
to NOC erros in REO ramap register cases. As in later point
of time packets will be coming on wrong reo2sw ring and at
the destination side channels are not enabled. When NOC error
happens the current system is of no help to root cause as the
write fail happened way before. So do panic if pci wake request
fails which help to root cause the reason for failure.
Change-Id: I30d3f0a7858f3d4af96a80f69ba59764c9a7c8e9
CRs-Fixed: 2541061
When txrx_stats 28 is issued we post messages to reo command ring
to receive reo queue stats on the reo status ring.
This leads to acces accessing reo_cmd_ring head pointer shadow
register when runtime pm is suspended. Perform
a hif_pm_runtime_get to resume the apps before accessing
the shadow register.
Change-Id: Ie6df817fc114bd4c8ba7783df1fe3bd770deec40
CRs-Fixed: 2544174
As a part of 802.11ax amendment, 6GHz band operation is added.
Since the 6 GHz channel numbers are overlapping with existing 2.4GHz
and 5GHz channel numbers, use frequency to identify unique channel
operation instead of channel number. Channel frequency is unique across
bands.
As part of above requirement add logic to process rx mgmt
packets based on the frequencies instead of channel numbers.
Change-Id: I33e31fa124cedfab31dd1827721a420ad6cdba07
CRs-Fixed: 2519512
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_timeout API
per chipset as the macro
to retrieve the flow_idx_timeout value is
chipset dependent.
Change-Id: I03030e3763b3c4a9099699a2d24b8110961610cf
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_invalid API
per chipset as the macro
to retrieve the flow_idx_invalid value is
chipset dependent.
Change-Id: I5b8622eb896456b7388016a16657048d0da4e970
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_get API
per chipset as the macro
to retrieve the flow_idx value is
chipset dependent.
Change-Id: I75131d7c048f5b67489ed25fbd52bfcf01bab782
CRs-Fixed: 2522133
Add the following macros:
1. HAL_REO_CONFIG
2. HAL_RX_MSDU_DESC_INFO_GET
3. HAL_RX_LINK_DESC_MSDU0_PTR
Add the relevant function pointers to
retrieve the descriptor info from the
above mentioned macros based on a
given chipset.
Change-Id: If44ae3d91397f1b1b0c36a49ce56a2c5e719434e
CRs-Fixed: 2522133
Add the following macros:
1. HAL_RX_GET_FC_VALID
2. HAL_RX_GET_TO_DS_FLAG
3. HAL_RX_GET_MAC_ADDR2_VALID
4. HAL_RX_GET_FILTER_CATEGORY
5. HAL_RX_GET_PPDU_ID
Also add function pointers to
retrieve the flags from the above
macros.
Change-Id: I334b198588ceba77cd30bdde7ebc500cdbe18358
CRs-Fixed: 2522133
Add the following HAL macros:
1. HAL_RX_MSDU0_BUFFER_ADDR_LSB
2. HAL_RX_MSDU_DESC_INFO_PTR_GET
3. HAL_ENT_MPDU_DESC_INFO
4. HAL_DST_MPDU_DESC_INFO
Add relevant function pointers to retrieve
descriptor info from the macros based
on chipsets.
Change-Id: I99ce7566a668180c7849eedea915b6f23a8dbf35
CRs-Fixed: 2522133
Implement hal_tx_desc_set_mesh_en API
based on the chipset as
the macro to set mesh_en value is
chipset dependent.
Change-Id: I43c85e4ed6fd4f9992de5b71857cdb8becd1dd36
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_sw_peer_id API
based on the chipset as
the macro to retrieve sa_sw_peer_id value is
chipset dependent.
Change-Id: I2efd1f851539bbffc8f75c7662045c1f4a3c4469
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_mpdu_qos_control_valid
API based on the chipset as
the macro to retrieve mpdu_qos_control value is
chipset dependent.
Change-Id: I61449ff5afc958f1a1f93013b0c5ab56d38cc833
CRs-Fixed: 2522133
Implement hal_reo_status_get_header_generic
based on the chipset as the macro to retrieve
reo_status value is chipset dependent.
Change-Id: I43bd624bec37fb051f33b4828fcf7cd3e4b2a61e
CRs-Fixed: 2522133
Implement hal_rx_hw_desc_get_ppduid API based
on the chipset as the macro to retrieve
ppduid value is chipset dependent.
Change-Id: I7d3457d731ea486f04367f98f9f18d3f1c0fcfd7
CRs-Fixed: 2522133
Implement hal_rx_tid_get API based on
the chipset as the macro to retrieve
tid value is chipset dependent.
Change-Id: I37eab3f3c1c2bbba6094b9ddb24d72712b819f73
CRs-Fixed: 2522133
Implement hal_rx_is_unicase API based
on the chipset as the macro to retrieve
is_unicast bit value is chipset dependent.
Change-Id: I38807f478c295309adf2a07ce9010b1bc04c734e
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_sequence_control_valid
API based on the chipset as
the macro to retrieve sequence control valid
value is chipset dependent.
Change-Id: I01a006094d0330060e9ff1a91200c48c2426f38d
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr4 API based
on the chipset as the macro to retrieve
addr4 value is chipset dependent.
Change-Id: Ie35d01de1619a8ab540bb1b2019a15b436efb7d4
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr3 API
based on the chipset as
the macro to retrieve addr3 value is
chipset dependent.
Change-Id: I3983599b656e82170de5905c08daee3ec164e7a0
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr2 API
based on the chipset as
the macro to retrieve addr2 value is
chipset dependent.
Change-Id: I4026db892d4f2f41db72c50f780ba898b8a17fa7
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr1 API
based on the chipset as the macro to
retrieve addr1 value is
chipset dependent.
Change-Id: I7ed88f2243d397c9d605a08d3b93e17f0004c63d
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_frame_control_valid API
based on the chipset as the macro to retrieve
frame control valid value is chipset dependent.
Change-Id: I49d16ae44b2e9567ff746d2088058f0c1025ea40
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_fr_ds API
based on the chipset as the macro to
retrieve for_ds value is chipset
dependent.
Change-Id: I6d41d02ac50cae752567d98645f0447cc122a84f
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_to_ds API based
on the chipset as the macro to retrieve
to_ds bit value is chipset dependent.
Change-Id: I36d9d14e226bcc604b91d8aecbe52836c5a12272
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_sw_peer_id API
based on the chipset as the macro to retrieve
sw_peer_id value is chipset dependent.
Change-Id: Ifebaf2430731f5e0593dde4789d721e9fe7ce7c1
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_mac_ad4_valid API
based on the chipset as the macro to retrieve
mac_ad4 value is chipset dependent.
Change-Id: I9d7cc90e798d4f0775e915fe6edcb1a1f5129490
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_last_msdu_get API
based on the chipset as the macro to retrieve
last_msdu value is chipset dependent.
Change-Id: I561c28a49062d7b650e68c5a4ce4da0183be34d6
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_dat API based on
the chipset as the macro to retrieve da_is_valid
value is chipset dependent.
Change-Id: I79f06eaa2576e7516c21f963b2c149aac7f62c64
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_first_msdu_get API
based on the chipset as the macro to retrieve
first_msdu value is chipset dependent.
Change-Id: Iea325159a0349c45a249c1ae113664c41a54b0f1
CRs-Fixed: 2522133
Implement hal_rx_print_pn API based on the
chipset as the macro to retrieve
pn value is chipset dependent.
Change-Id: Id9d0d3b34a5f6a09fe5903e1d24bb0a59205174b
CRs-Fixed: 2522133
Implement hal_rx_encryption_info API based
on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: I0c48800dfa5628898c53f7a9271e517b6bfa3da7
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_l3_hdr_padding_get API
based on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: Ice1fc2d70e339dc1d80fa6f34f37c5a7aa074be5
CRs-Fixed: 2522133
Implement hal_rx_desc_is_first_msdu API
based on the chipset as the macro to
retrieve first_msdu bit value is chipset
dependent.
Change-Id: I8e8a3aceb225b591b96e6f8453ffbebf1f78e529
CRs-Fixed: 2522133
