qcacmn: Add hal_rx_mpdu_start_mpdu_qos_control_valid_get API

Implement hal_rx_mpdu_start_mpdu_qos_control_valid
API based on the chipset as
the macro to retrieve mpdu_qos_control value is
chipset dependent.

Change-Id: I61449ff5afc958f1a1f93013b0c5ab56d38cc833
CRs-Fixed: 2522133

hal/wifi3.0/hal_internal.h

@@ -408,6 +408,7 @@ struct hal_hw_txrx_ops {
 	bool (*hal_rx_is_unicast)(uint8_t *buf);
 	uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
 	uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *hw_desc_addr);
+	uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
 };
 
 /**

hal/wifi3.0/hal_rx.h

@@ -1168,29 +1168,6 @@ hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
 	return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start);
 }
 
-/*
- * Get qos_control_valid from RX_MPDU_START
- */
-#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
-	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
-		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),		\
-		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK,		\
-		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
-
-static inline uint32_t
-hal_rx_mpdu_start_mpdu_qos_control_valid_get(uint8_t *buf)
-{
-	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
-	struct rx_mpdu_start *mpdu_start =
-			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
-	uint32_t qos_control_valid;
-
-	qos_control_valid = HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
-		&(mpdu_start->rx_mpdu_info_details));
-
-	return qos_control_valid;
-}
-
 /**
  * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO
  *
@@ -1214,6 +1191,34 @@ enum hal_rx_mpdu_info_sw_frame_group_id_type {
 	HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
 };
 
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get():
+ * Retrieve qos control valid bit from the tlv.
+ * @hal_soc_hdl: hal_soc handle
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get(
+				hal_soc_handle_t hal_soc_hdl,
+				uint8_t *buf)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	if ((!hal_soc) || (!hal_soc->ops)) {
+		hal_err("hal handle is NULL");
+		QDF_BUG(0);
+		return QDF_STATUS_E_INVAL;
+	}
+
+	if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
+		return hal_soc->ops->
+		       hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
+
+	return QDF_STATUS_E_INVAL;
+}
+
 /**
  * hal_rx_is_unicast: check packet is unicast frame or not.
  * @hal_soc_hdl: hal_soc handle

hal/wifi3.0/qca6290/hal_6290.c

@@ -707,6 +707,24 @@ static void hal_reo_status_get_header_6290(uint32_t *d, int b, void *h1)
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
 
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290():
+ * Retrieve qos control valid bit from the tlv.
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+
+	return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
+		&mpdu_start->rx_mpdu_info_details);
+}
+
 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
 	/* init and setup */
 	hal_srng_dst_hw_init_generic,
@@ -772,6 +790,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_6290,
 	hal_rx_tid_get_6290,
 	hal_rx_hw_desc_get_ppduid_get_6290,
+	hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290,
 };
 
 struct hal_hw_srng_config hw_srng_table_6290[] = {

hal/wifi3.0/qca6290/hal_6290_rx.h

@@ -221,6 +221,12 @@
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
 
+#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
+
 #if defined(QCA_WIFI_QCA6290_11AX)
 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\

hal/wifi3.0/qca6390/hal_6390.c

@@ -705,6 +705,23 @@ static void hal_reo_status_get_header_6390(uint32_t *d, int b, void *h1)
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
 
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390():
+ * Retrieve qos control valid bit from the tlv.
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+
+	return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
+		&mpdu_start->rx_mpdu_info_details);
+}
 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	/* init and setup */
 	hal_srng_dst_hw_init_generic,
@@ -770,6 +787,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_6390,
 	hal_rx_tid_get_6390,
 	hal_rx_hw_desc_get_ppduid_get_6390,
+	hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390,
 };
 
 struct hal_hw_srng_config hw_srng_table_6390[] = {

hal/wifi3.0/qca6390/hal_6390_rx.h

@@ -227,6 +227,12 @@
 	RX_MSDU_START_5_MIMO_SS_BITMAP_MASK,		\
 	RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
 
+#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
+
 /*
  * hal_rx_msdu_start_nss_get_6390(): API to get the NSS
  * Interval from rx_msdu_start

hal/wifi3.0/qca6490/hal_6490.c

@@ -610,6 +610,7 @@ static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1)
 	h->tstamp =
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
+
 struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
 	/* rx */
 	hal_rx_get_rx_fragment_number_6490,
@@ -635,4 +636,5 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_6490,
 	hal_rx_tid_get_6490,
 	hal_rx_hw_desc_get_ppduid_get_6490,
+	NULL,
 };

hal/wifi3.0/qca6490/hal_6490_rx.h

@@ -201,3 +201,9 @@
 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),	\
 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
+
+#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info)   \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
+		RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),\
+		RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,    \
+		RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB))

hal/wifi3.0/qca8074v1/hal_8074v1.c

@@ -702,6 +702,25 @@ static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1)
 	h->tstamp =
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
+
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1():
+ * Retrieve qos control valid bit from the tlv.
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+
+	return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
+		&mpdu_start->rx_mpdu_info_details);
+}
+
 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -768,6 +787,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_8074v1,
 	hal_rx_tid_get_8074v1,
 	hal_rx_hw_desc_get_ppduid_get_8074v1,
+	hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1,
 };
 
 struct hal_hw_srng_config hw_srng_table_8074[] = {

hal/wifi3.0/qca8074v1/hal_8074v1_rx.h

@@ -209,6 +209,12 @@
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),	\
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
+
+#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
 /*
  * hal_rx_msdu_start_nss_get_8074(): API to get the NSS
  * Interval from rx_msdu_start

hal/wifi3.0/qca8074v2/hal_8074v2.c

@@ -699,6 +699,25 @@ static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1)
 	h->tstamp =
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
+
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2():
+ * Retrieve qos control valid bit from the tlv.
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+
+	return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
+		&mpdu_start->rx_mpdu_info_details);
+}
+
 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -765,6 +784,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_8074v2,
 	hal_rx_tid_get_8074v2,
 	hal_rx_hw_desc_get_ppduid_get_8074v2,
+	hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2,
 };
 
 struct hal_hw_srng_config hw_srng_table_8074v2[] = {

hal/wifi3.0/qca8074v2/hal_8074v2_rx.h

@@ -218,6 +218,12 @@
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),	\
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
 		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
+
+#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,		\
+		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
 /*
  * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
  * Interval from rx_msdu_start

hal/wifi3.0/qcn9000/hal_9000.c

@@ -708,6 +708,25 @@ static void hal_reo_status_get_header_9000(uint32_t *d, int b, void *h1)
 	h->tstamp =
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
+
+/**
+ * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000():
+ * Retrieve qos control valid bit from the tlv.
+ * @buf: pointer to rx pkt TLV.
+ *
+ * Return: qos control value.
+ */
+static inline uint32_t
+hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+
+	return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
+		&mpdu_start->rx_mpdu_info_details);
+}
+
 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -774,6 +793,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 	hal_rx_is_unicast_9000,
 	hal_rx_tid_get_9000,
 	hal_rx_hw_desc_get_ppduid_get_9000,
+	hal_rx_mpdu_start_mpdu_qos_control_valid_9000,
 };
 
 struct hal_hw_srng_config hw_srng_table_9000[] = {