add kalama config file to all drivers' Kbuild, including soc/dsp/ipc
Change-Id: I56a6092da515f211a56617f0cff60079dbf0aa39
Signed-off-by: Junkai Cai <junkai@quicinc.com>
Sometimes after SSR/DPR is triggered, RX_TX_CORE_CLK, WSA_TX_CORE_CLK
and WSA2_TX_CORE_CLK are not reset which causes WSA or WCD not
detected. Make this change to add reset during SSR.
Change-Id: I343f2f92244de3eee844e220a6201b389dc647b4
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Add support to use 4p8MHz DAC rate for receiver over WSA.
Change-Id: Ia0811670326be8131687fbdff70464da063902b2
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Add changes to use wsa883x for receiver with
low_noise mode settings.
Change-Id: Icfa43ebbdb1e366f365053535f541bee03751ca3
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
When SWR MIC is used, lpass-cdc doesn't know if it's amic
or dmic on WCD. Add new mixer control to indicate if
swr_dmic is used or not.
Change-Id: I2910053d1da9110edfe9b021df744f9d1662d158
Signed-off-by: Meng Wang <mengw@codeaurora.org>
When adsp SSR happens, VA_MCLK enabled by VA_SWR_PWR widget will
not be disabled as ADSP is down and it cannot enable TX_MCLk before
disabling VA_MCLK. After disabling SVA, VA_MCLk is left open.
Add dev_up flag to indicate SSR and close VA_MCLK during SSR.
Change-Id: Ic544ce32c46054c7362d3eb07a4a47ec115d2651
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Thermal framework is expected an error to be returned if the requested
cur_state exceed the max_state.
Change-Id: I1e0d8124a1aa6c0d755b35225207638aefdcb464
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
Update central broadcast register control to enable bcl path.
Change-Id: Ibc05289d9cdd41e81369c6ef2547eceffa36d73a
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
When reading/writing lpass codec registers, pm_runtime_put_autosuspend
is missed when vote fails and it causes device fails suspending after
ssr. Add pm_runtime_put_autosuspend to pair with pm_runtime_get_sync.
When LPASS_CDC_MACRO_EVT_PRE_SSR_UP comes, core vote is needed before
resetting GFMUX reg and dev_up is not set to true yet. Add pre_dev_up
flag to indicate PRE_SSR_UP and be used in lpass_cdc_check_core_votes
to avoid false alarm.
Change-Id: Ic12ecd9645f291078e32f4921f9f77c2d85e4b8c
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Incorrect check for return value of clk_div_get
causes CLK_DIV2 setting being missed. Fix the
return value check to address this.
Change-Id: Ic1b6761ab836a38c657ac7e43efda0e2f23c5fee
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
During ssr, when powering down audio path and core vote fails,
it directly exits without disabling clock. After adsp is up,
it will enable both RX_MCLk and RX_TX_MCLK which causes
glitch on headset output.
Change-Id: I98d3cdbffa0a5ae1ac4064579a52a29b02d4ae3e
Signed-off-by: Deepali Jindal <deepjind@codeaurora.org>
SVA switch is not retain at VA_CLK when switch
between handset and headset mic sva. Update the
clock release logic during swr power event.
Change-Id: I52c5f7576426af2ff385a862da872e8d86959ecb
Signed-off-by: Meng Wang <mengw@codeaurora.org>
When requested clk is not default clk, it should not enable
VA_MCLk directly. lpass_cdc_clk_rsc_check_and_update_va_clk
will take care of VA_MCLK switch.
Change-Id: I602be7dcc0228fd2e6ecd7624a96663e89485bd0
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Add ftrace log to debug NOC issues.
When writing/reading lpass codec registers, add vote_lock
to make sure clk is not disabled.
Change-Id: I1df924d6aefee2899f7e5008851c1c324dabf62a
Signed-off-by: Meng Wang <mengw@codeaurora.org>
When multi wsas are connected to wsa-macro and some registers
are written to wsa, swr broadcast mode is used. When closing
one wsa, it will also send the register write to the other wsa
and it should not get updated. The other wsa will be in bad
state.
Remove broadcast for wsa-macro to resolve this issue.
Change-Id: I4c788a213fdcd217861703a13d44c096fd9b632d
Signed-off-by: Meng Wang <mengw@codeaurora.org>
During adsp SSR, after adsp is down, lpass_cdc_runtime_resume
is called in va-marco and fails. lpass_cdc_runtime_suspend is
not called 100ms later. After adsp is up and va-macro considers
lpass_cdc is resumed and not setting clk which causes wcd not
detected. Call runtime_suspend when vote fails to resolve
the issue.
Change-Id: Ice398d0168c5c67f6c98e3122af507ca74837175
Signed-off-by: Meng Wang <mengw@codeaurora.org>
cooling of WSA/WSA2 is to reduce the digital gain.
the cooling callback should only be called when the WSA pointer
has not been initialized.
Also the adjusted volume of RX0 and RX1 need to be set separately.
Change-Id: I6aac0e7a3a3219e8b5c24d711a6c7773824827e9
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
the dapm_mclk_enable flag has not been set back to false
when the actual mclk is disabled.
Change-Id: Ic04756b3dcd074887dd1e93f23cf31873abc1428
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
When WCD AMIC is used and connected to SWR master port3,
DMIC clk div is updated by mistake. Update logic to update
DMIC clk DIV with new flag.
Change-Id: Iee01acf97f925ec54c8d189c13e63acca7ffc2f4
Signed-off-by: Meng Wang <mengw@codeaurora.org>
The digital gain will be adjusted lower than what userspace set
during playback if the device temperature reach the threshold.
Whenever digital gain is changed from userspace, codec will check the cooling
state and adjust the gain.
Change-Id: I52df0f96cf20b90a9bdad70b9c117eed82145fb2
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
Because of a HW limitation in DSP, while switching
RCG from TX MCLK to VA MCLK for SVA use cases
a glitch is seen on AHB bus leading to data
corruption in registers.
So, while doing a mux switch for VA RCG clock selection,
do not configure the muxsel register in HLOS as it is
taken care in DSP itself as a workaround for HW limitation.
Change-Id: Ie36ff239689e634f5c29ad03b343b95de2d12547
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Check if clk is enabled before disabling it to avoid
warning log during adsp SSR.
Change-Id: I916af6f9efacfe3d08e0b05dcc0c6023944369d2
Signed-off-by: Meng Wang <mengw@codeaurora.org>
The PCM_RATE bit field in LPASS_TX_CDC_TXn_TX_PATH_CTL
ranges from 0 to 6.
In the current implementation of tx-macro, the value
read is mapped directly to the sample rate instead of
the indices. Change is to correct this.
Add the delay based on pcm_rate in va-macro as well.
Change-Id: I6cb7e58e71f2a25356608611f1dfed83171706f6
Signed-off-by: Soumya Managoli <smanag@codeaurora.org>
The number of HIFI FIR coeff will not be retained if power collapsed,
need to be written right before FIR_START is kicked off.
Change-Id: I034949eb7748f8b2e5b21445fa10f4f1df66a7bf
Previously code will not write coefficients if there are exactly 100 coeffs
in first coeffs write. Or if user update coeffs on the fly with one group
unchanged.
Change-Id: Id4e8af06dec6b247f4a79a797d5b61668fd1e7f4
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
Update regmap default entries of spk protection
registers as per lpass cdc version 2p5.
Change-Id: I7c966eb3edbe9a9c065c03220ef2b9390b1fc723
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Add wsa2 backend dai links only in platforms
which has 4 wsa speakers.
add 2 to the device index parsed from hardware device id
of wsa slave to match the dai names in the msm_dailink.h
Change-Id: Iffe43842123526f4925f9d5bcd8dff0317bac7a7
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
During sound card register init call, if swr pdev
is not initialized yet respective soundwire port
config is not updated to soundwire controller device.
In macro drivers, update swr pdev into macro private
data prior to platform device add.
Change-Id: Ifa67471cfc7a10b102b573df6285e598bb0b5e5e
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Enable HiFi FIR PCM filter on digital codec to support HiFi audio playback on headset.
Change-Id: I5bc03ed45a3fd149c93dc04f33be0a581b519d44
Signed-off-by: Junkai Cai <junkai@codeaurora.org>
Return from config compander during aux path powerup
as aux path compander is not present.
Change-Id: I5ed1557dddfb64c8712d92c75fd58aa98b96355d
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
