Revert "asoc: lpass-cdc: Do not update VA clk muxsel register"

This reverts commit 57fa62e29238c9f36b2f58135df564e7f88b8538.

Change-Id: I1afb0d2f7495d3b30fc99bb4391eda094921fa89
Signed-off-by: Meng Wang <[email protected]>

asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c

@@ -232,13 +232,11 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
 
 	if (enable) {
 		if (priv->clk_cnt[clk_id] == 0) {
-			if (clk_id != VA_CORE_CLK) {
-				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+			ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
 							default_clk_id,
 							true);
-				if (ret < 0)
-					goto done;
-			}
+			if (ret < 0)
+				goto done;
 
 			ret = clk_prepare_enable(priv->clk[clk_id]);
 			if (ret < 0) {
@@ -246,22 +244,14 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
 					__func__, clk_id);
 				goto err_clk;
 			}
-			/*
-			 * Temp SW workaround to address a glitch issue of
-			 * VA GFMux instance responsible for switching from
-			 * TX MCLK to VA MCLK. This configuration would be taken
-			 * care in DSP itself
-			 */
-			if (clk_id != VA_CORE_CLK) {
-				if (priv->dev_up_gfmux) {
-					iowrite32(0x1, clk_muxsel);
-					muxsel = ioread32(clk_muxsel);
-					trace_printk("%s: muxsel value after enable: %d\n",
-							__func__, muxsel);
-				}
-				lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
-							   false);
+			if (priv->dev_up_gfmux) {
+				iowrite32(0x1, clk_muxsel);
+				muxsel = ioread32(clk_muxsel);
+				trace_printk("%s: muxsel value after enable: %d\n",
+						__func__, muxsel);
 			}
+			lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
+							   false);
 		}
 		priv->clk_cnt[clk_id]++;
 	} else {
@@ -273,34 +263,24 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
 		}
 		priv->clk_cnt[clk_id]--;
 		if (priv->clk_cnt[clk_id] == 0) {
-			/*
-			 * Temp SW workaround to address a glitch issue
-			 * of VA GFMux instance responsible for
-			 * switching from TX MCLK to VA MCLK.
-			 * This configuration would be taken
-			 * care in DSP itself.
-			 */
-			if (clk_id != VA_CORE_CLK) {
-				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+			ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
 						default_clk_id, true);
-				if (!ret && priv->dev_up_gfmux) {
-					iowrite32(0x0, clk_muxsel);
-					muxsel = ioread32(clk_muxsel);
-					trace_printk("%s: muxsel value after disable: %d\n",
+			if (!ret && priv->dev_up_gfmux) {
+				iowrite32(0x0, clk_muxsel);
+				muxsel = ioread32(clk_muxsel);
+				trace_printk("%s: muxsel value after disable: %d\n",
 						__func__, muxsel);
-				}
 			}
 			clk_disable_unprepare(priv->clk[clk_id]);
-			if (clk_id != VA_CORE_CLK && !ret)
+			if (!ret)
 				lpass_cdc_clk_rsc_mux0_clk_request(priv,
-						default_clk_id, false);
+							default_clk_id, false);
 		}
 	}
 	return ret;
 
 err_clk:
-	if (clk_id != VA_CORE_CLK)
-		lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
+	lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
 done:
 	return ret;
 }