asoc: codecs: Initial lpass-cdc 2.6 implementation

Update register headers, add version 2.6 string.

Change-Id: I6236ddebba3fcbb37f2a64c8638d4eea4f6cc062
Signed-off-by: Matthew Rice <mrice@codeaurora.org>

asoc/codecs/lpass-cdc/lpass-cdc-registers.h

@@ -621,6 +621,7 @@
 #define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB	(WSA_START_OFFSET + 0x00D4)
 #define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB	(WSA_START_OFFSET + 0x00D8)
 #define LPASS_CDC_WSA_TOP_FS_UNGATE2		(WSA_START_OFFSET + 0x00DC)
+#define LPASS_CDC_WSA_TOP_SEQ_CTL0		(WSA_START_OFFSET + 0x00E0)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0	(WSA_START_OFFSET + 0x0100)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1	(WSA_START_OFFSET + 0x0104)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0	(WSA_START_OFFSET + 0x0108)
@@ -865,9 +866,68 @@
 #define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1	(WSA_START_OFFSET + 0x0A00)
 #define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2	(WSA_START_OFFSET + 0x0A04)
 #define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3	(WSA_START_OFFSET + 0x0A08)
-#define WSA_MAX_OFFSET				(WSA_START_OFFSET + 0x0A08)
+/* lpass 2.6 new registers */
+#define LPASS_CDC_WSA_PBR_PATH_CTL	(WSA_START_OFFSET + 0xB00)
+#define LPASS_CDC_WSA_LA_CFG	(WSA_START_OFFSET + 0xB04)
+#define LPASS_CDC_WSA_PBR_CFG1	(WSA_START_OFFSET + 0xB08)
+#define LPASS_CDC_WSA_PBR_CFG2	(WSA_START_OFFSET + 0xB0C)
+#define LPASS_CDC_WSA_PBR_CFG3	(WSA_START_OFFSET + 0xB10)
+#define LPASS_CDC_WSA_PBR_CFG4	(WSA_START_OFFSET + 0xB14)
+#define LPASS_CDC_WSA_PBR_CFG5	(WSA_START_OFFSET + 0xB18)
+#define LPASS_CDC_WSA_PBR_CFG6	(WSA_START_OFFSET + 0xB1C)
+#define LPASS_CDC_WSA_PBR_CFG7	(WSA_START_OFFSET + 0xB20)
+#define LPASS_CDC_WSA_PBR_CFG8	(WSA_START_OFFSET + 0xB24)
+#define LPASS_CDC_WSA_PBR_CFG9	(WSA_START_OFFSET + 0xB28)
+#define LPASS_CDC_WSA_PBR_CFG10	(WSA_START_OFFSET + 0xB2C)
+#define LPASS_CDC_WSA_PBR_CFG11	(WSA_START_OFFSET + 0xB30)
+#define LPASS_CDC_WSA_PBR_CFG12	(WSA_START_OFFSET + 0xB34)
+#define LPASS_CDC_WSA_PBR_CFG13	(WSA_START_OFFSET + 0xB38)
+#define LPASS_CDC_WSA_PBR_CFG14	(WSA_START_OFFSET + 0xB3C)
+#define LPASS_CDC_WSA_PBR_CFG15	(WSA_START_OFFSET + 0xB40)
+#define LPASS_CDC_WSA_PBR_CFG16	(WSA_START_OFFSET + 0xB44)
+#define LPASS_CDC_WSA_PBR_CFG17	(WSA_START_OFFSET + 0xB48)
+#define LPASS_CDC_WSA_ILIM_CFG0	(WSA_START_OFFSET + 0xB4C)
+#define LPASS_CDC_WSA_ILIM_CFG1	(WSA_START_OFFSET + 0xB50)
+#define LPASS_CDC_WSA_ILIM_CFG2	(WSA_START_OFFSET + 0xB54)
+#define LPASS_CDC_WSA_ILIM_CFG3	(WSA_START_OFFSET + 0xB58)
+#define LPASS_CDC_WSA_ILIM_CFG4	(WSA_START_OFFSET + 0xB5C)
+#define LPASS_CDC_WSA_ILIM_CFG5	(WSA_START_OFFSET + 0xB60)
+#define LPASS_CDC_WSA_ILIM_CFG6	(WSA_START_OFFSET + 0xB64)
+#define LPASS_CDC_WSA_ILIM_CFG7	(WSA_START_OFFSET + 0xB68)
+#define LPASS_CDC_WSA_ILIM_CFG8	(WSA_START_OFFSET + 0xB6C)
+#define LPASS_CDC_WSA_LA_CFG_1	(WSA_START_OFFSET + 0xB70)
+#define LPASS_CDC_WSA_PBR_CFG1_1	(WSA_START_OFFSET + 0xB74)
+#define LPASS_CDC_WSA_PBR_CFG2_1	(WSA_START_OFFSET + 0xB78)
+#define LPASS_CDC_WSA_PBR_CFG3_1	(WSA_START_OFFSET + 0xB7C)
+#define LPASS_CDC_WSA_PBR_CFG4_1	(WSA_START_OFFSET + 0xB80)
+#define LPASS_CDC_WSA_PBR_CFG5_1	(WSA_START_OFFSET + 0xB84)
+#define LPASS_CDC_WSA_PBR_CFG6_1	(WSA_START_OFFSET + 0xB88)
+#define LPASS_CDC_WSA_PBR_CFG7_1	(WSA_START_OFFSET + 0xB8C)
+#define LPASS_CDC_WSA_PBR_CFG8_1	(WSA_START_OFFSET + 0xB90)
+#define LPASS_CDC_WSA_PBR_CFG9_1	(WSA_START_OFFSET + 0xB94)
+#define LPASS_CDC_WSA_PBR_CFG10_1	(WSA_START_OFFSET + 0xB98)
+#define LPASS_CDC_WSA_PBR_CFG11_1	(WSA_START_OFFSET + 0xB9C)
+#define LPASS_CDC_WSA_PBR_CFG12_1	(WSA_START_OFFSET + 0xBA0)
+#define LPASS_CDC_WSA_PBR_CFG13_1	(WSA_START_OFFSET + 0xBA4)
+#define LPASS_CDC_WSA_PBR_CFG14_1	(WSA_START_OFFSET + 0xBA8)
+#define LPASS_CDC_WSA_PBR_CFG15_1	(WSA_START_OFFSET + 0xBAC)
+#define LPASS_CDC_WSA_PBR_CFG16_1	(WSA_START_OFFSET + 0xBB0)
+#define LPASS_CDC_WSA_ILIM_CFG0_1	(WSA_START_OFFSET + 0xBB4)
+#define LPASS_CDC_WSA_ILIM_CFG1_1	(WSA_START_OFFSET + 0xBB8)
+#define LPASS_CDC_WSA_ILIM_CFG2_1	(WSA_START_OFFSET + 0xBBC)
+#define LPASS_CDC_WSA_ILIM_CFG5_1	(WSA_START_OFFSET + 0xBC0)
+#define LPASS_CDC_WSA_ILIM_CFG9	(WSA_START_OFFSET + 0xBC4)
+#define LPASS_CDC_WSA_ILIM_CFG6_1	(WSA_START_OFFSET + 0xBC8)
+#define LPASS_CDC_WSA_PBR_CFG18	(WSA_START_OFFSET + 0xBCC)
+#define LPASS_CDC_WSA_PBR_CFG18_1	(WSA_START_OFFSET + 0xBD0)
+#define LPASS_CDC_WSA_PBR_CFG19	(WSA_START_OFFSET + 0xBD4)
+#define LPASS_CDC_WSA_PBR_CFG20	(WSA_START_OFFSET + 0xBD8)
+#define LPASS_CDC_WSA_PBR_CFG21	(WSA_START_OFFSET + 0xBDC)
+#define LPASS_CDC_WSA_PBR_CFG22	(WSA_START_OFFSET + 0xBE0)
+#define LPASS_CDC_WSA_PBR_CFG23	(WSA_START_OFFSET + 0xBE4)
+#define WSA_MAX_OFFSET				(WSA_START_OFFSET + 0xBE4)
 
-#define LPASS_CDC_WSA_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
+#define LPASS_CDC_WSA_MACRO_MAX 0x2FA /* 0xBE4/4 = 0x2F9 + 1 registers */
 
 /* VA macro registers */
 #define VA_START_OFFSET				0x3000
@@ -895,6 +955,7 @@
 #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1	(VA_START_OFFSET + 0x00D4)
 #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2	(VA_START_OFFSET + 0x00D8)
 #define LPASS_CDC_VA_TOP_CSR_SWR_CTRL		(VA_START_OFFSET + 0x00DC)
+#define LPASS_CDC_VA_TOP_CSR_SEQ_CTL0		(VA_START_OFFSET + 0x00E0)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0	(VA_START_OFFSET + 0x0100)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1	(VA_START_OFFSET + 0x0104)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0	(VA_START_OFFSET + 0x0108)
@@ -983,6 +1044,7 @@
 #define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB	(WSA2_START_OFFSET + 0x00D4)
 #define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB	(WSA2_START_OFFSET + 0x00D8)
 #define LPASS_CDC_WSA2_TOP_FS_UNGATE2		(WSA2_START_OFFSET + 0x00DC)
+#define LPASS_CDC_WSA2_TOP_SEQ_CTL0		(WSA2_START_OFFSET + 0x00E0)
 #define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0	(WSA2_START_OFFSET + 0x0100)
 #define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1	(WSA2_START_OFFSET + 0x0104)
 #define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0	(WSA2_START_OFFSET + 0x0108)
@@ -1227,9 +1289,69 @@
 #define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1	(WSA2_START_OFFSET + 0x0A00)
 #define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2	(WSA2_START_OFFSET + 0x0A04)
 #define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3	(WSA2_START_OFFSET + 0x0A08)
-#define WSA2_MAX_OFFSET				(WSA2_START_OFFSET + 0x0A08)
+/* lpass 2.6 new registers */
+#define LPASS_CDC_WSA2_PBR_PATH_CTL	(WSA2_START_OFFSET + 0xB00)
+#define LPASS_CDC_WSA2_LA_CFG	(WSA2_START_OFFSET + 0xB04)
+#define LPASS_CDC_WSA2_PBR_CFG1	(WSA2_START_OFFSET + 0xB08)
+#define LPASS_CDC_WSA2_PBR_CFG2	(WSA2_START_OFFSET + 0xB0C)
+#define LPASS_CDC_WSA2_PBR_CFG3	(WSA2_START_OFFSET + 0xB10)
+#define LPASS_CDC_WSA2_PBR_CFG4	(WSA2_START_OFFSET + 0xB14)
+#define LPASS_CDC_WSA2_PBR_CFG5	(WSA2_START_OFFSET + 0xB18)
+#define LPASS_CDC_WSA2_PBR_CFG6	(WSA2_START_OFFSET + 0xB1C)
+#define LPASS_CDC_WSA2_PBR_CFG7	(WSA2_START_OFFSET + 0xB20)
+#define LPASS_CDC_WSA2_PBR_CFG8	(WSA2_START_OFFSET + 0xB24)
+#define LPASS_CDC_WSA2_PBR_CFG9	(WSA2_START_OFFSET + 0xB28)
+#define LPASS_CDC_WSA2_PBR_CFG10	(WSA2_START_OFFSET + 0xB2C)
+#define LPASS_CDC_WSA2_PBR_CFG11	(WSA2_START_OFFSET + 0xB30)
+#define LPASS_CDC_WSA2_PBR_CFG12	(WSA2_START_OFFSET + 0xB34)
+#define LPASS_CDC_WSA2_PBR_CFG13	(WSA2_START_OFFSET + 0xB38)
+#define LPASS_CDC_WSA2_PBR_CFG14	(WSA2_START_OFFSET + 0xB3C)
+#define LPASS_CDC_WSA2_PBR_CFG15	(WSA2_START_OFFSET + 0xB40)
+#define LPASS_CDC_WSA2_PBR_CFG16	(WSA2_START_OFFSET + 0xB44)
+#define LPASS_CDC_WSA2_PBR_CFG17	(WSA2_START_OFFSET + 0xB48)
+#define LPASS_CDC_WSA2_ILIM_CFG0	(WSA2_START_OFFSET + 0xB4C)
+#define LPASS_CDC_WSA2_ILIM_CFG1	(WSA2_START_OFFSET + 0xB50)
+#define LPASS_CDC_WSA2_ILIM_CFG2	(WSA2_START_OFFSET + 0xB54)
+#define LPASS_CDC_WSA2_ILIM_CFG3	(WSA2_START_OFFSET + 0xB58)
+#define LPASS_CDC_WSA2_ILIM_CFG4	(WSA2_START_OFFSET + 0xB5C)
+#define LPASS_CDC_WSA2_ILIM_CFG5	(WSA2_START_OFFSET + 0xB60)
+#define LPASS_CDC_WSA2_ILIM_CFG6	(WSA2_START_OFFSET + 0xB64)
+#define LPASS_CDC_WSA2_ILIM_CFG7	(WSA2_START_OFFSET + 0xB68)
+#define LPASS_CDC_WSA2_ILIM_CFG8	(WSA2_START_OFFSET + 0xB6C)
+#define LPASS_CDC_WSA2_LA_CFG_1	(WSA2_START_OFFSET + 0xB70)
+#define LPASS_CDC_WSA2_PBR_CFG1_1	(WSA2_START_OFFSET + 0xB74)
+#define LPASS_CDC_WSA2_PBR_CFG2_1	(WSA2_START_OFFSET + 0xB78)
+#define LPASS_CDC_WSA2_PBR_CFG3_1	(WSA2_START_OFFSET + 0xB7C)
+#define LPASS_CDC_WSA2_PBR_CFG4_1	(WSA2_START_OFFSET + 0xB80)
+#define LPASS_CDC_WSA2_PBR_CFG5_1	(WSA2_START_OFFSET + 0xB84)
+#define LPASS_CDC_WSA2_PBR_CFG6_1	(WSA2_START_OFFSET + 0xB88)
+#define LPASS_CDC_WSA2_PBR_CFG7_1	(WSA2_START_OFFSET + 0xB8C)
+#define LPASS_CDC_WSA2_PBR_CFG8_1	(WSA2_START_OFFSET + 0xB90)
+#define LPASS_CDC_WSA2_PBR_CFG9_1	(WSA2_START_OFFSET + 0xB94)
+#define LPASS_CDC_WSA2_PBR_CFG10_1	(WSA2_START_OFFSET + 0xB98)
+#define LPASS_CDC_WSA2_PBR_CFG11_1	(WSA2_START_OFFSET + 0xB9C)
+#define LPASS_CDC_WSA2_PBR_CFG12_1	(WSA2_START_OFFSET + 0xBA0)
+#define LPASS_CDC_WSA2_PBR_CFG13_1	(WSA2_START_OFFSET + 0xBA4)
+#define LPASS_CDC_WSA2_PBR_CFG14_1	(WSA2_START_OFFSET + 0xBA8)
+#define LPASS_CDC_WSA2_PBR_CFG15_1	(WSA2_START_OFFSET + 0xBAC)
+#define LPASS_CDC_WSA2_PBR_CFG16_1	(WSA2_START_OFFSET + 0xBB0)
+#define LPASS_CDC_WSA2_ILIM_CFG0_1	(WSA2_START_OFFSET + 0xBB4)
+#define LPASS_CDC_WSA2_ILIM_CFG1_1	(WSA2_START_OFFSET + 0xBB8)
+#define LPASS_CDC_WSA2_ILIM_CFG2_1	(WSA2_START_OFFSET + 0xBBC)
+#define LPASS_CDC_WSA2_ILIM_CFG5_1	(WSA2_START_OFFSET + 0xBC0)
+#define LPASS_CDC_WSA2_ILIM_CFG9	(WSA2_START_OFFSET + 0xBC4)
+#define LPASS_CDC_WSA2_ILIM_CFG6_1	(WSA2_START_OFFSET + 0xBC8)
+#define LPASS_CDC_WSA2_PBR_CFG18	(WSA2_START_OFFSET + 0xBCC)
+#define LPASS_CDC_WSA2_PBR_CFG18_1	(WSA2_START_OFFSET + 0xBD0)
+#define LPASS_CDC_WSA2_PBR_CFG19	(WSA2_START_OFFSET + 0xBD4)
+#define LPASS_CDC_WSA2_PBR_CFG20	(WSA2_START_OFFSET + 0xBD8)
+#define LPASS_CDC_WSA2_PBR_CFG21	(WSA2_START_OFFSET + 0xBDC)
+#define LPASS_CDC_WSA2_PBR_CFG22	(WSA2_START_OFFSET + 0xBE0)
+#define LPASS_CDC_WSA2_PBR_CFG23	(WSA2_START_OFFSET + 0xBE4)
 
-#define LPASS_CDC_WSA2_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
+#define WSA2_MAX_OFFSET				(WSA2_START_OFFSET + 0xBE4)
+
+#define LPASS_CDC_WSA2_MACRO_MAX 0x2FA /* 0xBE4/4 = 0x2F9 + 1 registers */
 
 #define LPASS_CDC_MAX_REGISTER WSA2_MAX_OFFSET
 

asoc/codecs/lpass-cdc/lpass-cdc-regmap.c

@@ -556,7 +556,8 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT, 0x00},
 	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB, 0x00},
 	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB, 0x00},
-	{ LPASS_CDC_WSA_TOP_FS_UNGATE2, 0x03},
+	{ LPASS_CDC_WSA_TOP_FS_UNGATE2, 0x1F},
+	{ LPASS_CDC_WSA_TOP_SEQ_CTL0, 0x00},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
@@ -771,6 +772,65 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
 	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
 	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
+	/* lpass 2.6 new registers */
+	{ LPASS_CDC_WSA_PBR_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA_LA_CFG, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG2, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG3, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG4, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG5, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG6, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG7, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG8, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG9, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG10, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG11, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG12, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG13, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG14, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG15, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG16, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG17, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG0, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG2, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG3, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG4, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG5, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG6, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG7, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG8, 0x00},
+	{ LPASS_CDC_WSA_LA_CFG_1, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG1_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG2_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG3_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG4_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG5_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG6_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG7_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG8_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG9_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG10_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG11_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG12_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG13_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG14_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG15_1, 0xFF},
+	{ LPASS_CDC_WSA_PBR_CFG16_1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG0_1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG1_1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG2_1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG5_1, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG9, 0x00},
+	{ LPASS_CDC_WSA_ILIM_CFG6_1, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG18, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG18_1, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG19, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG20, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG21, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG22, 0x00},
+	{ LPASS_CDC_WSA_PBR_CFG23, 0x00},
 
 	/* VA macro */
 	{ LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -795,6 +855,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
 	{ LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
 	{ LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
+	{ LPASS_CDC_VA_TOP_CSR_SEQ_CTL0, 0x00},
 
 	/* VA core */
 	{ LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
@@ -879,6 +940,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB, 0x00},
 	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB, 0x00},
 	{ LPASS_CDC_WSA2_TOP_FS_UNGATE2, 0x03},
+	{ LPASS_CDC_WSA2_TOP_SEQ_CTL0, 0x00},
 	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0, 0x00},
 	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1, 0x00},
 	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0, 0x00},
@@ -1093,6 +1155,65 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
 	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
 	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
+	/* lpass 2.6 new registers */
+	{ LPASS_CDC_WSA2_PBR_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_LA_CFG, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG2, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG3, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG4, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG5, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG6, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG7, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG8, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG9, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG10, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG11, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG12, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG13, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG14, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG15, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG16, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG17, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG2, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG3, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG4, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG5, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG6, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG7, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG8, 0x00},
+	{ LPASS_CDC_WSA2_LA_CFG_1, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG1_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG2_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG3_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG4_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG5_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG6_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG7_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG8_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG9_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG10_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG11_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG12_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG13_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG14_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG15_1, 0xFF},
+	{ LPASS_CDC_WSA2_PBR_CFG16_1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG0_1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG1_1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG2_1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG5_1, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG9, 0x00},
+	{ LPASS_CDC_WSA2_ILIM_CFG6_1, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG18, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG18_1, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG19, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG20, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG21, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG22, 0x00},
+	{ LPASS_CDC_WSA2_PBR_CFG23, 0x00},
 };
 
 static bool lpass_cdc_is_readable_register(struct device *dev,

asoc/codecs/lpass-cdc/lpass-cdc-tables.c

@@ -556,6 +556,7 @@ u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SEQ_CTL0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
@@ -639,6 +640,7 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SEQ_CTL0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
@@ -854,6 +856,65 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
+	/* lpass 2.6 new registers */
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_LA_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG17)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG6)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG7)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG8)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_LA_CFG_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG1_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG2_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG3_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG4_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG5_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG6_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG7_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG8_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG9_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG10_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG11_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG12_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG13_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG14_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG15_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG16_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG0_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG1_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG2_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG5_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_ILIM_CFG6_1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG18)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG18_1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG19)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG20)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG21)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG22)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_PBR_CFG23)] = RD_WR_REG,
 };
 
 u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = {
@@ -884,6 +945,7 @@ u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SEQ_CTL0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
@@ -1099,6 +1161,66 @@ u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
+	/* lpass 2.6 new registers */
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_LA_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG17)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG6)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG7)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG8)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_LA_CFG_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG1_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG2_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG3_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG4_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG5_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG6_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG7_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG8_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG9_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG10_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG11_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG12_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG13_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG14_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG15_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG16_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG0_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG1_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG2_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG5_1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_ILIM_CFG6_1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG18)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG18_1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG19)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG20)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG21)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG22)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_PBR_CFG23)] = RD_WR_REG,
+
 };
 
 u8 *lpass_cdc_reg_access[MAX_MACRO] = {

asoc/codecs/lpass-cdc/lpass-cdc.c

@@ -820,6 +820,9 @@ static ssize_t lpass_cdc_version_read(struct snd_info_entry *entry,
 	case LPASS_CDC_VERSION_2_5:
 		len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_2_5\n");
 		break;
+	case LPASS_CDC_VERSION_2_6:
+		len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_2_6\n");
+		break;
 	default:
 		len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
 	}
@@ -1099,7 +1102,7 @@ static int lpass_cdc_soc_codec_probe(struct snd_soc_component *component)
 {
 	struct lpass_cdc_priv *priv = dev_get_drvdata(component->dev);
 	int macro_idx, ret = 0;
-	u8 core_id_0 = 0, core_id_1 = 0;
+	u8 core_id_0 = 0, core_id_1 = 0, core_id_2 = 0;
 
 	snd_soc_component_init_regmap(component, priv->regmap);
 
@@ -1124,12 +1127,16 @@ static int lpass_cdc_soc_codec_probe(struct snd_soc_component *component)
 					LPASS_CDC_VA_TOP_CSR_CORE_ID_0);
 	core_id_1 = snd_soc_component_read(component,
 					LPASS_CDC_VA_TOP_CSR_CORE_ID_1);
+	core_id_2 = snd_soc_component_read(component,
+					LPASS_CDC_VA_TOP_CSR_CORE_ID_2);
 	if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
 		priv->version = LPASS_CDC_VERSION_2_0;
 	if ((core_id_0 == 0x02) && (core_id_1 == 0x0E))
 		priv->version = LPASS_CDC_VERSION_2_1;
 	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F))
 		priv->version = LPASS_CDC_VERSION_2_5;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x60 || core_id_2 == 0x61))
+		priv->version = LPASS_CDC_VERSION_2_6;
 
 	/* call init for supported macros */
 	for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {

asoc/codecs/lpass-cdc/lpass-cdc.h

@@ -14,6 +14,7 @@
 #define LPASS_CDC_VERSION_2_0 0x0004
 #define LPASS_CDC_VERSION_2_1 0x0005
 #define LPASS_CDC_VERSION_2_5 0x0006
+#define LPASS_CDC_VERSION_2_6 0x0007
 
 enum {
 	START_MACRO,