Install volatile enum and range properties for UCSC IGC, GC, UNMULT
and ALPHA_DITHER. This will mark the force dirty property data as
true, and will avoid caching in driver by always applying the
property values set by userspace, rather than checking for modified
values.
Change-Id: Ib8132165fb58ddc829bf8610657e302e0798d72f
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Add debug log to dump qtimer information after the input hw-fence
signal configuration.
Change-Id: I7617b1a6bae3db1e003c42bfe306dbe7f552ad83
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add display event log for the display input hw-fence.
Change-Id: Id0fc19565c7b83c8009ab518dae7323db534b66e
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Force vbif axi halt on all the power-collapse with/without RSC.
This will keep the logic simple for all targets.
Change-Id: I5a4956cbc1f5875d923d5cf818016fba7ed2c8f7
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When precise vsync timestamp feature is enabled, move the vblank
signaling from interrupt context to event thread. This helps in
freeing up the interrupt context soon. The precise vsync timestamp
feature along with DRM hooks to get the vblank timestamp will get
the correct timestamp though the event thread is scheduled later.
Change-Id: I77002913f222ff422b6118f9fc952533065c07aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Enable the Expected Present Time feature in sde catalog
for pineapple target.
Change-Id: I12a6abb00e8792564fad390be1d49e3217f88517
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Time the flush bit setting to match with the expected frame
rate. To achieve this, introduce a new connector property called
“Expected_Present_Time”. User space will set it based on the
intended content fps and AVR step, relative to the last retire
fence timestamp as calculated by user space. Delay the frame
trigger to match with the EPT.
Change-Id: I0b86caaa53ee2e37671167acdffd22ec62b4e9ae
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Modify the default INTF TE sync threshold config in cmd-mode to
32-bit max based on the INTF TE 32-bit support.
Change-Id: I963ffa8ae37bce0e85deb335609857c17e32d6b0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the
trigger window to be out of sync when power is restored
until the next vsync is received.
This change reads the panel read pointer and overrrides
the internal register to allow a frame to be picked up in
the current vsync cycle, but defers it to next vsync if it
comes later than the safe trigger window.
Change-Id: I741a91edcddc105eda34d875e8e1c32933b83d71
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Current driver prints error messages when it fails
registration for the display clients with the hw-fence
driver, however, this is not an error as currently
feature is disabled by default in hw-fence driver,
which as result will fail registration for clients.
Therefore, silent the error messages for a failed
registration.
Change-Id: I13b872db3452a57a885c73cc8f1cf512be986dd0
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add rc feature disable handling in case set rc feature fails.
This will disable rc feature for all instances if set rc feature
fails for any instance.
Change-Id: I159b9bd3ed1416c4b2d32440d10132cb024f9529
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Timing DB needs to be disabled after panel vnsyc.
Update the wait time to reflect difference in line time
between MDP and panel vsync.
Change-Id: Ib5282d67995e8379ead928218f31a8f9fe7fa978
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Currently when calculating interface timing value, driver uses
drm_mode_vrefresh API which uses the mode clock and mode timing
values to determine the vertical refresh rate.
On a dual-DSI panel, the mode clock is calculated based on the full
display width which causes the interface vrefresh value to be 2x
greater than what it is supposed to be.
This change uses the cached_mode value, which has the correct
interface based mode clock.
Change-Id: I51bccf4962ec802b37e1ee9a463bfc08f162e5d6
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Remove debug info log and extra braces
from UCSC code.
Change-Id: I3dcd01aaebdeda81c08d3724e65f13ee7959ef5c
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
This change adds support for dynamically enabling and disabling
additional physical encoder IRQs.
Change-Id: I500fa69d1b8b8df39fd608391c906257efdea63b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Correcting the string name of UCSC in the register dump.
Change-Id: I2c8976d6d9bf4804ed6454b848c4a3b326b56f54
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
Add a debugfs node to set maximum bpp for the base panel which will
be used in both SST and MST use cases to limit the bpp.
Change-Id: I0ef7866e2b82a2078d6cdf97ee0d7226c2125b21
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
add memory barrier before and after last command to avoid
out of order packet queuing to lut dma packet queue.
add memory barrier after ctrl flush to ensure lut dma
trigger, dspp flush and ctrl flush all are written to dpu
before control start.
Change-Id: I7e1613034af8407d55529cf3f95c70994334af82
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
DSI PHY isolation is unused and considered deprecated. Previous uses
were for power measurements and emulated platform support. Use on
emulated platforms has been supplanted by PHY PLL bypass.
Change-Id: I547681912ff82f0df09a1b98c671eac32c19412a
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
MDSS 10.0 supports additional dedicated cwb pingpong pair.
This change updates downscaler block mux programming to
support when second dcwb pinpong pair is in use.
Change-Id: I1d5bdb557132c56874b13d06b9fe1aafeaadb36a
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Current dpu hw settings do not match the protocol id with
the ipcc hw protocol id for the fencing protocol.
This change adjusts the programming of the dpu configuration
register to properly select and use the fencing protocol.
Change-Id: I253c15856b8b3baaa3780681d953c2e79a30d686
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Enable hw-fence driver for Display in pineapple.
This change only allows Display to import the
hw-fence driver api's, but does not enable the
feature by default. Enablement of the feature in
the driver is done through the device tree property.
Change-Id: I4fe97e0cc76f780d1326a69c4162dc4908e89724
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
devm_of_pwm_get is deprecated and need to change
to devm_pwm_get.
Change-Id: Ibeee90261ff40dc50b6a5e40e583bee11a5b177c
Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
