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603 Incheckningar

Upphovsman SHA1 Meddelande Datum
Bojun Pan
d71131b194 msm: ipa: add ipa pkt threshold functionality
ioctl interface to config the pkt threshold.

Change-Id: I71c037d17d14283bdcf456a255259fca42040821
2021-05-12 14:46:30 -07:00
Bojun Pan
358648ec10 msm: ipa: revert "add ipa pkt threshold functionality"
This reverts commit c1c1fd1cf3.

Change-Id: Ice7ace5dbd7d3bfdf9fc6280cdefa8ab5d806932
2021-05-12 14:36:42 -07:00
qctecmdr
fc1ef37e26 Merge "ip-accelerator: Add kernel-test to verify dynamic FLT table move" 2021-05-12 07:50:01 -07:00
qctecmdr
37553a788a Merge "msm: ipa: Clear IEOB for stopped channels with MSI IRQ" 2021-05-12 06:21:23 -07:00
qctecmdr
607b84c377 Merge "msm: ipa: enable multi queue on rmnet_ipa0" 2021-05-12 05:45:14 -07:00
qctecmdr
bb7b7dc551 Merge "msm:ipa: don't assert on wrong flt parameters" 2021-05-12 05:07:33 -07:00
Sivan Reinstein
aad6531b8d ip-accelerator: Add kernel-test to verify dynamic FLT table move
Verify dynamic move of FLT table between SRAM and DDR

Change-Id: Ib4d3248697dc7c9d484163cbf827e809697b8c84
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-12 12:15:04 +03:00
qctecmdr
506114ab6c Merge "msm: ipa4: Add changes to support PCIe addr for WDI2 over GSI" 2021-05-11 23:05:28 -07:00
Sivan Reinstein
2a9bd8f3af msm: ipa: Clear IEOB for stopped channels with MSI IRQ
Clear IEOBs as part of CH stop for channels with MSI IRQ type

Change-Id: I7b9af7f385b0876fc2f43314bd3588110911a021
Acked-by: Nadav Levintov <nadav@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-11 22:51:29 -07:00
qctecmdr
84a087fefa Merge "msm: ipa4: Enable dynamic switch between WDI2 and WDI3" 2021-05-11 22:27:35 -07:00
qctecmdr
56f3b1c620 Merge "msm: ipa3: new low latency data pipes support" 2021-05-11 21:50:59 -07:00
qctecmdr
23bbb03606 Merge "IPA: ipa3_tx_dp remove redundant variable" 2021-05-11 13:28:48 -07:00
Amir Levy
8f6db82c32 IPA: ipa3_tx_dp remove redundant variable
Removing a variable which was only set to NULL and later "freed".

Change-Id: I4973f8f2850669b9092eddee6d4179ab2089f227
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-05-11 06:19:33 -07:00
Amir Levy
b14a195498 msm: IPA: ULSO LAN USB - RNDIS driver change
Support for ULSO LAN USB use case in rndis datapath.

Change-Id: I2035e5fcc7c927cc3e5d7f5652fb017c304b5ad5
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-05-11 05:49:50 -07:00
Ashok Vuyyuru
581d69866d msm: ipa3: Changes to keep IPA clock voted in panic notifier
Adding changes to avoid unclocked access in panic notifier.
Increasing the IPA clock vote before saving the IPA registers.

Change-Id: Ie055ffa844df45b8a65603190495bc2d1cc3f84a
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-10 22:30:59 -07:00
Michael Adisumarta
91efd29ef8 msm: ipa3: new low latency data pipes support
Includes low latency data pipe definition and
support for waipio.

Change-Id: I0158eb15b38de0dfd2b0052b699c69a7c7f58fa1
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-05-10 17:21:49 -07:00
qctecmdr
92a085730d Merge "msm: ipa: add ipa pkt threshold functionality" 2021-05-10 10:18:40 -07:00
qctecmdr
aeea2f09f3 Merge "msm: ipa3: Adding chnages to update event RP from DDR" 2021-05-10 08:58:37 -07:00
Pooja Kumari
2a84451352 msm: ipa4: Add changes to support PCIe addr for WDI2 over GSI
Add changes to support PCIe addr for WDI2 over GSI.

Change-Id: Ibdf9e577990f9036fb22fa09378f47bbda37defa
Signed-off-by: Pooja Kumari <kumarip@codeaurora.org>
2021-05-10 04:58:52 -07:00
Pooja Kumari
0a25f1ce91 msm: ipa4: Enable dynamic switch between WDI2 and WDI3
Make change in techpack to enable WDI2 and
dynamic switching between WDI3 and WDI2
based on wlan input.

Change-Id: Ifa7fb2798e937cf8d0f0fadf7b204106a0eb4ce0
Signed-off-by: Pooja Kumari <kumarip@codeaurora.org>
2021-05-10 04:58:28 -07:00
qctecmdr
83f25ced0b Merge "msm: ipa: support new qmi request for hw filter stats info" 2021-05-09 14:56:03 -07:00
qctecmdr
3c771ef777 Merge "msm: ipa5: avoid NULL access in qmi_send_req_wait" 2021-05-07 19:45:37 -07:00
qctecmdr
9f9419fbae Merge "msm: ipa: update IPA clock plan for 5.1" 2021-05-07 17:37:56 -07:00
qctecmdr
ee167d89ca Merge "ipa: Take care of header table corner cases" 2021-05-07 01:48:17 -07:00
qctecmdr
db830a061d Merge "msm: ipa3: Changes to check disconnect in progress while sending data" 2021-05-06 15:48:04 -07:00
qctecmdr
68d72628a0 Merge "msm: ipa: page pool recycling enhancements" 2021-05-06 15:13:00 -07:00
Ashok Vuyyuru
d5c796665b msm: ipa3: Changes to check disconnect in progress while sending data
In SSR scenario while teardown the pipe there could be possibility to
receive the UL data to avoid queuing the data checking for disconnect
InProgress flag.

Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
Change-Id: I73397e51e6e7affae71313d08356f809788db484
2021-05-06 10:25:23 -07:00
Ashok Vuyyuru
9ea98412c7 msm: ipa3: Adding chnages to update event RP from DDR
In suspend scenario while checking channel empty scenario
updating the event ring RP pointer from direct register, it
may cause mismatch in reading in polling context. To avoid
discrepancy  reading RP pointer DDR location.

Change-Id: Ie198ea9ace033e31463acd974f10dccdcac45c55
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-06 22:50:16 +05:30
Amir Levy
a779045daa msm:ipa: don't assert on wrong flt parameters
If given flt parameters are wrong, there is no need to
assert, just return an error.

Change-Id: I130b94928b2f1959585d5288fd1577d706424761
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-05-06 10:00:40 -07:00
qctecmdr
5f833251e9 Merge "ipa-kernel-tests: Add ULSO to EP config" 2021-05-06 05:39:11 -07:00
qctecmdr
a5f12fda5d Merge "ipa: Do not commit partial only headers" 2021-05-06 01:55:33 -07:00
Ilia Lin
809e12ad09 ipa-kernel-tests: Add ULSO to EP config
Change-Id: Id8f5e0db58b1ec3e72dbe6457b7338f19eaa29ea
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 23:51:06 -07:00
qctecmdr
389f327c0f Merge "msm:ipa: DDR to SRAM optimization for eth" 2021-05-05 15:47:03 -07:00
qctecmdr
5e63fdb447 Merge "msm: ipa: Enable GSI Channel almost empty Feature" 2021-05-05 15:11:15 -07:00
Chaitanya Pratapa
ac6f7e39fb msm: ipa: enable multi queue on rmnet_ipa0
Enable multi-queue on rmnet_ipa0 to segregate LL traffic
from default traffic. Default traffic uses rx-0 and LL
traffic uses rx-1.

Change-Id: I438497a44555455721162fc696a3565b3f2cd1b6
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-05-05 11:16:23 -07:00
qctecmdr
432970c45d Merge "msm: ipa3: add ipa sw-flt functionality" 2021-05-05 09:51:12 -07:00
qctecmdr
6066a1fe88 Merge "ipa: Add debugfs for header table offsets" 2021-05-05 07:40:38 -07:00
Ilia Lin
e50b7af7ea ipa: Take care of header table corner cases
In case of a system that doesn't have SRAM or DDR area
designated for the header table, additional checks are required.

Change-Id: I841f1a17d2996dee87676e4a1c04f49ec2a30d5f
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 14:43:33 +03:00
Skylar Chang
6a4dff1d40 msm: ipa3: add ipa sw-flt functionality
Add sw-flt support to specify the mac,
ip segments and ifaces to route to SW-path.

Change-Id: I95afe23e9e335d3a55d7cb560e4e7d369f747688
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2021-05-05 04:11:44 -07:00
qctecmdr
1a6a777b9f Merge "ipa: Move kernel-tests from ip_accelerator to techpack." 2021-05-05 04:08:10 -07:00
qctecmdr
f8025918f9 Merge "ipa: Add ipanat library to the techpack." 2021-05-05 03:30:25 -07:00
Ilia Lin
e3ce2f25dc ipa: Add debugfs for header table offsets
Print used and free offset sizes in the header table debugfs

Change-Id: I56ab0a9f607dc45d3a83a4e3749370b02caf7a0a
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 10:28:42 +03:00
Ilia Lin
f1c1fb3a16 ipa: Move kernel-tests from ip_accelerator to techpack.
Move ip_accelerator which is a part of kernel-tests-internal
from kernel to techpack. Updated up to SHA1:
b8790774643dbfea5b312ed422ef86b54e4c8d7f

The kernel-test-module was moved into the driver,
and will be compiled as part of debug build.

Change-Id: I427b9ea061401c74845d2bd0d505da747d5fe89f
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-04 20:50:23 -07:00
Ilia Lin
5faad0ab9e ipa: Add ipanat library to the techpack.
Moving the ipanat library sources from the ipacm project to here.
The library will be compiled separately and will be common
for the ipacm and ipa-kernel-tests.

Change-Id: I01becf981e15ea0c2958423585ea487affb421d0
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 06:48:22 +03:00
qctecmdr
e7414c97c6 Merge "msm: ipa: add unit tests for NTN3 offload" 2021-05-04 19:03:59 -07:00
qctecmdr
52ccb99a40 Merge "msm: ipa: Workaround for MHI target" 2021-05-04 19:03:59 -07:00
Michael Adisumarta
9fe77b2f6f msm: ipa: support new qmi request for hw filter stats info
Includes qmi req ipa_filter_stats_info_type_v01 for
the ipa_filter_stats_info_type_v01.

Change-Id: I015479b02c2c92f6ed048caac0d46d51f96102e8
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-05-04 14:15:11 -07:00
Chaitanya Pratapa
3b6a63ab7c msm: ipa: page pool recycling enhancements
Added the following enhancements to page pool recycling logic.

1) Common page pool for coalescing/default pipe.
2) Common page pool will hold 5 times the rx_pool_sz (224) for page
   recycling pool and 3 times for temp pool. This is done to sustain
   50 stream scenarios.

Change-Id: I55adfffa101df33c46e95b0214fb7338644e8d7c
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-05-04 11:24:47 -07:00
Bojun Pan
c1c1fd1cf3 msm: ipa: add ipa pkt threshold functionality
ioctl interface to config the pkt threshold.

Change-Id: Ic48910518dde12e7466ebbf78d9e77c5ea7d92d3
2021-05-04 10:47:36 -07:00
qctecmdr
fbfd385847 Merge "ipa: Distribute header table on SRAM and DDR" 2021-05-04 09:14:06 -07:00