Mix path clk is gated by main path clk, as per current logic we are not
enabling main path clk for mix path use-cases.
Enable main path clk before enabling mix path for UPD dedicated backend
to work.
Change-Id: I209d1eaf25f4ef08bbd534f5ecc858e465ce7e18
Signed-off-by: Faiz Nabi Kuchay <quic_fkuchay@quicinc.com>
Currently on pineapple CDP platform, sbu1/2 switches are always
pre-connected to gnd/mic of the jack. Avoid this static connection
and connect/disconnect only when headset insertion/removal is detected.
Change-Id: If3bef6834caeb539492304d8b16808cd09c5afab
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
Updated WCD937x, WSA881x-analog and bolero drivers for successful
compilation on kernel6.0 for holi.
Change-Id: Ia91a999f825570b3d7123842f0aad3740c4d25ed
In PDR cases INTR_CLEAR registers values are not updating
properly while doing reg_cache in recover from PDR. So add
these registers as volatile to get the exact HW values.
When these registe values are properly updated the FSM_PA
status is reseting properly and working.
Change-Id: I8fa7b01b3256ec8f01edc3fe48a519accfff9638
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
In SSR/PDR usb switch settings won't be reset in wcd939x-i2c
driver. So no need to do switch settings for AATC when recovering
from SSR/PDR. Depends on the status to avoid AATC switch settings
again after SSR/PDR.
Change-Id: If7fc2a84356a406e9cf7e6cc557e19584fda3969
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Add static variable to store version to avoid improper
device pointer in wcd939x_readable_register().
Update WCD939X_NUM_REGISTERS macro to be correct size.
Change-Id: Ib594f2f799ac2202ff78c02ccf2f6cdb80ffd38e
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Few register default values are incorrectly set for harmonium
codec in the register map table. Fix it by setting correct
values as per the hardware interface documentation.
Change-Id: Ibcb517d6050a4932243ead396e6f89294aab4a23
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
During spk playback and VA concurrency,
sometimes WSA CLK goes out of sync causing
VI_TX data mute. To resolve this, everytime
after WSA MCLK enable toggle fs_cnt_clr bit.
Change-Id: Ia936f1d4843890d2ae5c02b039f502941a5427b9
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
Check and update register sequences for wcd9395 version
2.0.
Change-Id: I85fc739744ee2ba2c5dbdc853eb639b84cac6478
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
enable l_det_en bit while detecting the HS.
Issue: While removing HS some additional electrical interrupts
are triggered and reporting different events to userspace, which is
cause issues. To avoid this electrical interrupt flow, there is
a check in adc_hs_rem_irq for wcd_swch_level_remove() to check
for l_det_en bit status. Depends on this it will return from the
adc_hs_rem_irq() without going further.
Solution: Enabling the l_det_en bit will helps to avoid serving
electrical interrupt flow to further in adc_hs_rem_irq().So this
will helps to stop reporting different/unwanted events to user space.
Change-Id: I29d72b65ebb59969b69f3f8c7f4c7eb2debb0f1c
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
During some concurrencies even though we are not
enabling the swrm port, we are trying to disable it.
which causes problem w.r.t clock disablement,
To avoid that we are updating the set bit only
when port is enabled, based on that bit we are taking
decision to disable or enable the port.
Change-Id: I6707c56c40dd3716917edc097c4b7bcad68261fd
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Add scale and alpha register value updates based
on computed digital xtalk cancellation gain.
Change-Id: I8c12e2ba7c1566476741fec5459a74549f19cf5f
Signed-off-by: Sam Rainey <quic_rainey@quicinc.com>
Update wcd939x-usbss mode on PA enable and disable.
Change-Id: I73a19ea73102ced5c8011a5a1567ebfa372b2e44
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
usbc USCI event gets called and removal is reported, where bit
0 of mbhc->intr_status i.e. (WCD_MBHC_ELEC_HS_INS) will be set to 0.
So in adc_hs_ins_irq() we can check if the WCD_MBHC_ELEC_HS_INS bit
is 0 or not, if 0 we just ignore the and return.
Change-Id: I5a7753a077f53c5cd26c8ad199899ff9c81ef7b8
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
enable the wsa and wsa2 clk as per sequence.
Change-Id: Ieefa4b6ea7aec535d940d780b0ed923483b4d3ee
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Remove drivers/clk/qcom/common.h, which is an
internal header that is unused in audio-ext-clk-up.c.
Change-Id: I62dbdfd87c717ec60461a32505cba1b603c5e512
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Harmonium supports full and half rate modes for DAC.
Update DAC rate to swr clkdiv2 to achieve better
power performance.
Change-Id: I136a064dc258ee839ea78c9f1051ba34521ac871
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
Get the wcd939x power mode of from mixer ctls and configure
same power mode to wcd-usbss.
Change-Id: I9dc8fe586f7e7608da542b0986bb7c605fc552d4
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
